dts: clock: SAM D5x/E5x: add more functionality

Add more functionality in clock control driver.
Add bindings for dfll, fdpll, gclk generator, mclk cpu, osc32k, rtc clock
and xosc.

Signed-off-by: Sunil Abraham <[email protected]>

Author: sunil-abraham

dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x.dtsi

@@ -42,12 +42,43 @@
 			      <0x40001400 0x20>, <0x40001c00 0x140>;
 			reg-names = "mclk", "oscctrl",
 				    "osc32kctrl", "gclk";
+			interrupts = <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>;
+
+			xosc: xosc {
+				compatible = "microchip,sam-d5x-e5x-xosc";
+			};
+
+			dfll: dfll {
+				compatible = "microchip,sam-d5x-e5x-dfll";
+			};
+
+			fdpll: fdpll {
+				compatible = "microchip,sam-d5x-e5x-fdpll";
+			};
+
+			rtcclock: rtcclock {
+				compatible = "microchip,sam-d5x-e5x-rtc";
+				#clock-cells = <1>;
+			};
+
+			xosc32k: xosc32k {
+				compatible = "microchip,sam-d5x-e5x-xosc32k";
+			};
+
+			gclkgen: gclkgen {
+				compatible = "microchip,sam-d5x-e5x-gclkgen";
+			};
 
 			gclkperiph: gclkperiph {
 				compatible = "microchip,sam-d5x-e5x-gclkperiph";
 				#clock-cells = <1>;
 			};
 
+			mclkcpu: mclkcpu {
+				compatible = "microchip,sam-d5x-e5x-mclkcpu";
+				mclk-cpu-div = <1>;
+			};
+
 			mclkperiph: mclkperiph {
 				compatible = "microchip,sam-d5x-e5x-mclkperiph";
 				#clock-cells = <1>;

dts/bindings/clock/microchip,sam-d5x-e5x-gclkperiph.yaml

@@ -21,3 +21,6 @@ properties:
 
       Driver waits in clock on API to check if the clock is actually on,
       so that the waiting time is not indefinite.
+
+# flash wait states need not be changed for this device, since automatic wait state generation
+# is enabled by default.

dts/bindings/clock/microchip,sam-d5x-e5x-clock.yaml renamed to dts/bindings/clock/microchip/sam_d5x_e5x/microchip,sam-d5x-e5x-clock.yaml

@@ -0,0 +1,169 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+title: SAM_D5x_E5x Internal Oscillator (OSC48M)
+
+description: |
+  Digital Frequency-Locked Loop (DFLL48M) configuration.
+
+include: [base.yaml]
+
+compatible: "microchip,sam-d5x-e5x-dfll"
+
+properties:
+  dfll-on-demand-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      0: The oscillator is always on
+      1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
+      clock source. The oscillator is not running if no peripheral is requesting the clock source.
+      Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait for
+      the clock to be on, if there is no peripheral request for the clock in the sequence of clock
+      Initialization. If required, better to turn on the clock using API, instead of enabling both
+      during startup.
+
+  dfll-run-in-standby-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      0: The DFLL is not running in standby sleep mode if no peripheral requests the clock.
+      1: The DFLL is running in standby sleep mode.
+      If ONDEMAND is one, the DFLL will be running when a peripheral is requesting the clock. If
+      ONDEMAND is false, the clock source will always be running in standby sleep mode.
+
+  dfll-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 1
+    description: |
+      Oscillator Enable
+      0: to disable, 1: to enable
+
+  dfll-wait-lock-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      If enabled, clock available only after DFLL is locked (Fine lock)
+      0: to disable, 1: to enable
+
+  dfll-bypass-coarse-lock-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      To bypass coarse lock procedure
+      0: to disable, 1: to enable
+
+  dfll-quick-lock-dis:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      Disable quick lock
+      1: to disable, 0: to enable
+
+  dfll-chill-cycle-dis:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      Disable chill cycle
+      1: to disable, 0: to enable
+
+  dfll-usb-recovery-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      Enable USB Clock Recovery Mode
+      0: to disable, 1: to enable
+
+  dfll-lose-lock-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      If enabled, locks will be lost after waking up from sleep modes,
+      if the DFLL clock has been stopped
+      0: Locks will not be lost after waking up from sleep modes
+      1: Locks will be lost after waking up from sleep modes
+
+  dfll-stable-freq-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      0: FINE calibration tracks changes in output frequency.
+      1: FINE calibration register value will be fixed after a fine lock.
+
+  dfll-closed-loop-en:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      0: The DFLL operates in open-loop operation.
+      1: The DFLL operates in closed-loop operation.
+
+  dfll-coarse-max-step:
+    type: int
+    default: 0
+    description: |
+      Indicates the maximum step size allowed during coarse adjustment in closed-loop mode (0 - 31)
+
+  dfll-fine-max-step:
+    type: int
+    default: 0
+    description: |
+      Indicates the maximum step size allowed during fine adjustment in closed-loop mode (0 - 255)
+
+  dfll-multiply-factor:
+    type: int
+    default: 0
+    description: |
+      Determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency (0
+      - 65535)
+
+  dfll-src-gclk:
+    type: string
+    enum:
+      - "gclk0"
+      - "gclk1"
+      - "gclk2"
+      - "gclk3"
+      - "gclk4"
+      - "gclk5"
+      - "gclk6"
+      - "gclk7"
+      - "gclk8"
+      - "gclk9"
+      - "gclk10"
+      - "gclk11"
+    default: "gclk0"
+    description: |
+      Reference source clock selection from gclk generator