arch: arm: cortex_a_r: add Kconfig options for cache segregation

On Arm Cortex R52, cache segregation policy controls the
number of L1 I/D cache ways that are allocated to Flash
and AXIM interface. Adding Kconfig options for configuring
it.

Writing to IMP_CSCTRL is only permitted before the caches
have been enabled, following a system reset.

Signed-off-by: Dat Nguyen Duy <[email protected]>

Author: Dat-NguyenDuy

arch/arm/core/cortex_a_r/Kconfig

@@ -111,6 +111,32 @@ config CPU_CORTEX_R52
 	help
 	  This option signifies the use of a Cortex-R52 CPU
 
+config CPU_CORTEX_R52_CACHE_SEGREGATION
+	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
+	depends on CPU_CORTEX_R52
+	help
+	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
+	  Updates to the cache segregation controls are only permitted before the caches
+	  have ever been enabled, following a system reset, otherwise the update is ignored.
+
+config CPU_CORTEX_R52_ICACHE_FLASH_WAY
+	int "L1 I-Cache Flash way"
+	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
+	range 0 4
+	default 0
+	help
+	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
+	  I-Cache ways are allocated for AXIM interface.
+
+config CPU_CORTEX_R52_DCACHE_FLASH_WAY
+	int "L1 D-Cache Flash way"
+	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
+	range 0 4
+	default 0
+	help
+	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
+	  all D-Cache ways are allocated for AXIM interface.
+
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R

arch/arm/core/cortex_a_r/reset.S

@@ -56,9 +56,12 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
     cmp r0, #MODE_HYP
     bne EL1_Reset_Handler
 
-    /* Init HSCTLR see Armv8-R AArch32 architecture profile */
-    ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
-    mcr p15, 4, r0, c1, c0, 0
+    /*
+     * The HSCTLR register provides top-level control of system operation in Hyp mode.
+     * Since the OS is not running in Hyp mode, and considering the Armv8-R AArch32
+     * architecture profile, there's no need to modify HSCTLR configuration unless
+     * Fast Interrupts need to be enabled.
+     */
 
     /* Init HACTLR: Enable EL1 access to all IMP DEF registers */
     ldr r0, =HACTLR_INIT
@@ -200,6 +203,12 @@ EL1_Reset_Handler:
 
 #endif /* CONFIG_DCLS */
 
+#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION)
+    ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY,
+                        CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY)
+    mcr p15, 1, r0, c9, c1, 0
+#endif
+
     ldr r0, =arm_cpu_boot_params
 
 #if CONFIG_MP_MAX_NUM_CPUS > 1

include/zephyr/arch/arm/cortex_a_r/cpu.h

@@ -56,6 +56,12 @@
 #define SCTLR_C_BIT		BIT(2)
 #define SCTLR_I_BIT		BIT(12)
 
+/* Armv8-R Cortex-R52 Cache Segregation Control Register */
+#define IMP_CSCTLR_DFLW_SHIFT	(0)
+#define IMP_CSCTLR_IFLW_SHIFT	(8)
+#define IMP_CSCTLR(iway, dway)  ((iway << IMP_CSCTLR_IFLW_SHIFT) | \
+				((dway << IMP_CSCTLR_DFLW_SHIFT)))
+
 /* Hyp System Control Register */
 #define HSCTLR_RES1		(BIT(29) | BIT(28) | BIT(23) | \
 				 BIT(22) | BIT(18) | BIT(16) | \