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drivers: fpga controller: add eos_s3 fpga driver
This adds driver for EOS_S3 SoC FPGA. Signed-off-by: Mateusz Sierszulski <[email protected]> Signed-off-by: Tomasz Gorochowik <[email protected]>
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‎CODEOWNERS‎

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/drivers/flash/ @nashif @nvlsianpu
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/drivers/flash/*b91* @yurvyn
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/drivers/flash/*nrf* @nvlsianpu
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/drivers/fpga/ @tgorochowik @kgugala
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/drivers/gpio/ @mnkp
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/drivers/gpio/*b91* @yurvyn
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/drivers/gpio/*lmp90xxx* @henrikbrixandersen

‎boards/arm/quick_feather/quick_feather.dts‎

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label = "User Push Button 0";
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};
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};
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fpga {
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status = "okay";
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};
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};
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&cpu0 {

‎drivers/fpga/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_EOS_S3_FPGA fpga_eos_s3.c)

‎drivers/fpga/Kconfig‎

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module-str = fpga
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source "subsys/logging/Kconfig.template.log_config"
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source "drivers/fpga/Kconfig.eos_s3"
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endif # FPGA

‎drivers/fpga/Kconfig.eos_s3‎

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# FPGA EOS S3 driver configuration options
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config EOS_S3_FPGA
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bool "EOS S3 fpga driver"
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help
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Enable EOS S3 FPGA driver.

‎drivers/fpga/fpga_eos_s3.c‎

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/*
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* Copyright (c) 2021 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <string.h>
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#include <device.h>
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#include <drivers/fpga.h>
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#include "fpga_eos_s3.h"
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void eos_s3_fpga_enable_clk(void)
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{
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CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON;
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CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON;
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CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON;
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CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_ON;
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}
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void eos_s3_fpga_disable_clk(void)
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{
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CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_OFF;
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CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_OFF;
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CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_OFF | C09_CLK_GATE_PATH_2_OFF;
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CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_OFF;
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}
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struct quickfeather_fpga_data {
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char *FPGA_info;
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};
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static enum FPGA_status eos_s3_fpga_get_status(const struct device *dev)
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{
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ARG_UNUSED(dev);
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if (PMU->FB_STATUS == FPGA_STATUS_ACTIVE) {
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return FPGA_STATUS_ACTIVE;
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} else
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return FPGA_STATUS_INACTIVE;
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}
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static const char *eos_s3_fpga_get_info(const struct device *dev)
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{
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struct quickfeather_fpga_data *data = dev->data;
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return data->FPGA_info;
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}
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static int eos_s3_fpga_on(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_ACTIVE) {
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return 0;
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}
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/* wake up the FPGA power domain */
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PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_FB_WU;
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while (PMU->FFE_FB_PF_SW_WU == PMU_FFE_FB_PF_SW_WU_FB_WU) {
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/* The register will clear itself if the FPGA starts */
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};
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eos_s3_fpga_enable_clk();
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/* enable FPGA programming */
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PMU->GEN_PURPOSE_0 = FB_CFG_ENABLE;
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PIF->CFG_CTL = CFG_CTL_LOAD_ENABLE;
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return 0;
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}
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static int eos_s3_fpga_off(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return 0;
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}
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PMU->FB_PWR_MODE_CFG = PMU_FB_PWR_MODE_CFG_FB_SD;
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PMU->FFE_FB_PF_SW_PD = PMU_FFE_FB_PF_SW_PD_FB_PD;
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eos_s3_fpga_disable_clk();
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return 0;
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}
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static int eos_s3_fpga_reset(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_ACTIVE) {
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eos_s3_fpga_off(dev);
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}
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eos_s3_fpga_on(dev);
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return -EAGAIN;
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}
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return 0;
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}
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static int eos_s3_fpga_load(const struct device *dev, uint32_t *image_ptr, uint32_t img_size)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return -EINVAL;
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}
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volatile uint32_t *bitstream = (volatile uint32_t *)image_ptr;
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for (uint32_t chunk_cnt = 0; chunk_cnt < (img_size / 4); chunk_cnt++) {
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PIF->CFG_DATA = *bitstream;
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bitstream++;
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}
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/* disable FPGA programming */
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PMU->GEN_PURPOSE_0 = FB_CFG_DISABLE;
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PIF->CFG_CTL = CFG_CTL_LOAD_DISABLE;
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PMU->FB_ISOLATION = FB_ISOLATION_DISABLE;
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return 0;
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}
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static int eos_s3_fpga_init(const struct device *dev)
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{
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IO_MUX->PAD_19_CTRL = PAD_ENABLE;
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struct quickfeather_fpga_data *data = dev->data;
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data->FPGA_info = FPGA_INFO;
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eos_s3_fpga_reset(dev);
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return 0;
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}
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static struct quickfeather_fpga_data fpga_data;
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static const struct fpga_driver_api eos_s3_api = {
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.reset = eos_s3_fpga_reset,
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.load = eos_s3_fpga_load,
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.get_status = eos_s3_fpga_get_status,
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.on = eos_s3_fpga_on,
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.off = eos_s3_fpga_off,
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.get_info = eos_s3_fpga_get_info
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};
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DEVICE_DEFINE(fpga, "FPGA", &eos_s3_fpga_init, NULL, &fpga_data, NULL, APPLICATION,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &eos_s3_api);

‎drivers/fpga/fpga_eos_s3.h‎

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/*
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* Copyright (c) 2021 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
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#define ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
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#include <eoss3_dev.h>
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struct PIF_struct {
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/* Fabric Configuration Control Register, offset: 0x000 */
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__IO uint32_t CFG_CTL;
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/* Maximum Bit Length Count, offset: 0x004 */
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__IO uint32_t MAX_BL_CNT;
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/* Maximum Word Length Count, offset: 0x008 */
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__IO uint32_t MAX_WL_CNT;
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uint32_t reserved[1020];
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/* Configuration Data, offset: 0xFFC */
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__IO uint32_t CFG_DATA;
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};
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#define PIF ((struct PIF_struct *)PIF_CTRL_BASE)
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#define FB_CFG_ENABLE ((uint32_t)(0x00000200))
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#define FB_CFG_DISABLE ((uint32_t)(0x00000000))
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#define CFG_CTL_APB_CFG_WR ((uint32_t)(0x00008000))
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#define CFG_CTL_APB_CFG_RD ((uint32_t)(0x00004000))
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#define CFG_CTL_APB_WL_DIN ((uint32_t)(0x00003C00))
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#define CFG_CTL_APB_PARTIAL_LOAD ((uint32_t)(0x00000200))
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#define CFG_CTL_APB_BL_SEL ((uint32_t)(0x00000100))
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#define CFG_CTL_APB_BLM_SEL ((uint32_t)(0x00000080))
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#define CFG_CTL_APB_BR_SEL ((uint32_t)(0x00000040))
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#define CFG_CTL_APB_BRM_SEL ((uint32_t)(0x00000020))
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#define CFG_CTL_APB_TL_SEL ((uint32_t)(0x00000010))
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#define CFG_CTL_APB_TLM_SEL ((uint32_t)(0x00000008))
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#define CFG_CTL_APB_TR_SEL ((uint32_t)(0x00000004))
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#define CFG_CTL_APB_TRM_SEL ((uint32_t)(0x00000002))
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#define CFG_CTL_APB_SEL_CFG ((uint32_t)(0x00000001))
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#define FB_ISOLATION_ENABLE ((uint32_t)(0x00000001))
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#define FB_ISOLATION_DISABLE ((uint32_t)(0x00000000))
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#define PMU_FFE_FB_PF_SW_PD_FB_PD ((uint32_t)(0x00000002))
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#define PMU_FB_PWR_MODE_CFG_FB_SD ((uint32_t)(0x00000002))
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#define PMU_FB_PWR_MODE_CFG_FB_DP ((uint32_t)(0x00000001))
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#define FPGA_INFO \
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"eos_s3 eFPGA features:\n" \
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"891 Logic Cells\n" \
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"8 FIFO Controllers\n" \
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"32 Configurable Interfaces\n" \
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"2x32x32(or 4x16x16) Multiplier\n" \
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"64Kbit SRAM\n"
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#define PAD_ENABLE \
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(PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL | PAD_SMT_DISABLE | PAD_REN_DISABLE | \
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PAD_SR_SLOW | PAD_CTRL_SEL_AO_REG)
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#define PAD_DISABLE \
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(PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW | PAD_E_4MA | PAD_P_PULLDOWN | \
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PAD_OEN_NORMAL | PAD_CTRL_SEL_AO_REG)
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#define CFG_CTL_LOAD_ENABLE \
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(CFG_CTL_APB_CFG_WR | CFG_CTL_APB_WL_DIN | CFG_CTL_APB_BL_SEL | CFG_CTL_APB_BLM_SEL | \
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CFG_CTL_APB_BR_SEL | CFG_CTL_APB_BRM_SEL | CFG_CTL_APB_TL_SEL | CFG_CTL_APB_TLM_SEL | \
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CFG_CTL_APB_TR_SEL | CFG_CTL_APB_TRM_SEL | CFG_CTL_APB_SEL_CFG)
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#define CFG_CTL_LOAD_DISABLE 0
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#endif /* ZEPHYR_DRIVERS_FPGA_EOS_S3_H_ */

‎samples/drivers/fpga/fpga_controller/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.13)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(fpga_controller)
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target_sources(app PRIVATE src/main.c)

‎samples/drivers/fpga/fpga_controller/README.md‎

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# Zephyr FPGA controller
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This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
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This sample demonstrates how to use the FPGA driver API.
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Currently the sample works with [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board).
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## Requirements
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* Zephyr RTOS
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* [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board)
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## Building
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For the QuickLogic QuickFeather board:
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```bash
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west build -b quick_feather samples/drivers/fpga/fpga_controller
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```
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## Running
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See [QuickFeather programming and debugging](https://docs.zephyrproject.org/latest/boards/arm/quick_feather/doc/index.html#programming-and-debugging) on how to load an image to the board.
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## Sample output
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Once the board is programmed, the LED should alternately flash red and green.

‎samples/drivers/fpga/fpga_controller/prj.conf‎

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CONFIG_FPGA=y
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CONFIG_EOS_S3_FPGA=y

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