xtensa: Enable userspace

Userspace support for Xtensa architecture using Xtensa MMU.

Some considerations:

- Syscalls are not inline functions like in other architectures because
  some compiler issues when using multiple registers to pass parameters
  to the syscall. So here we have a function call so we can use
  registers as we need.
- TLS is not supported by xcc in xtensa and reading PS register is
  a privileged instruction. So, we have to use threadptr to know if a
  thread is an user mode thread.

Signed-off-by: Flavio Ceolin <[email protected]>
Signed-off-by: Daniel Leung <[email protected]>

Author: Flavio Ceolin

arch/Kconfig

@@ -125,6 +125,7 @@ config XTENSA
 	select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
 	select ARCH_HAS_CODE_DATA_RELOCATION
 	select ARCH_HAS_TIMING_FUNCTIONS
+	select ARCH_MEM_DOMAIN_DATA if USERSPACE
 	imply ATOMIC_OPERATIONS_ARCH
 	help
 	  Xtensa architecture

arch/xtensa/Kconfig

@@ -113,6 +113,7 @@ config XTENSA_MMU
 	bool "Xtensa MMU Support"
 	default n
 	select MMU
+	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
 	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
 	select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE
 	help
@@ -144,8 +145,18 @@ if XTENSA_MMU
 		  The bit shift number for the virtual address for Xtensa
 		  page table (PTEVADDR).
 
+	config XTENSA_MMU_NUM_L1_TABLES
+		int "Number of L1 page tables"
+		default 1 if !USERSPACE
+		default 4
+		help
+		  This option specifies the maximum number of traslation tables.
+		  Translation tables are directly related to the number of
+		  memory domains in the target, considering the kernel itself requires one.
+
 	config XTENSA_MMU_NUM_L2_TABLES
 		int "Number of L2 page tables"
+		default 20 if USERSPACE
 		default 10
 		help
 		  Each table can address up to 4MB memory address.
@@ -159,6 +170,15 @@ if XTENSA_MMU
 
 endif # XTENSA_MMU
 
+config XTENSA_SYSCALL_USE_HELPER
+	bool "Use userspace syscall helper"
+	default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc-clang"
+	depends on USERSPACE
+	help
+	  Use syscall helpers for passing more then 3 arguments.
+	  This is a workaround for toolchains where they have
+	  issue modeling register usage.
+
 endif # CPU_HAS_MMU
 
 endmenu

arch/xtensa/core/CMakeLists.txt

@@ -22,6 +22,8 @@ zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
 zephyr_library_sources_ifdef(CONFIG_TIMING_FUNCTIONS timing.c)
 zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
 zephyr_library_sources_ifdef(CONFIG_XTENSA_MMU xtensa_mmu.c)
+zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
+zephyr_library_sources_ifdef(CONFIG_XTENSA_SYSCALL_USE_HELPER syscall_helper.c)
 
 zephyr_library_sources_ifdef(
   CONFIG_KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK

arch/xtensa/core/fatal.c

@@ -15,6 +15,7 @@
 #endif
 #endif
 #include <zephyr/debug/coredump.h>
+#include <zephyr/arch/common/exc_handle.h>
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
@@ -120,6 +121,14 @@ void z_xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
 	z_fatal_error(reason, esf);
 }
 
+#ifdef CONFIG_USERSPACE
+Z_EXC_DECLARE(z_xtensa_user_string_nlen);
+
+static const struct z_exc_handle exceptions[] = {
+	Z_EXC_HANDLE(z_xtensa_user_string_nlen)
+};
+#endif /* CONFIG_USERSPACE */
+
 #ifdef XT_SIMULATOR
 void exit(int return_code)
 {

arch/xtensa/core/include/xtensa_mmu_priv.h

@@ -18,18 +18,37 @@
 #define Z_XTENSA_PTE_VPN_MASK 0xFFFFF000U
 #define Z_XTENSA_PTE_PPN_MASK 0xFFFFF000U
 #define Z_XTENSA_PTE_ATTR_MASK 0x0000000FU
+#define Z_XTENSA_PTE_ATTR_CACHED_MASK 0x0000000CU
 #define Z_XTENSA_L1_MASK 0x3FF00000U
 #define Z_XTENSA_L2_MASK 0x3FFFFFU
 
 #define Z_XTENSA_PPN_SHIFT 12U
 
 #define Z_XTENSA_PTE_RING_MASK 0x00000030U
+#define Z_XTENSA_PTE_RING_SHIFT 4U
 
 #define Z_XTENSA_PTE(paddr, ring, attr) \
 	(((paddr) & Z_XTENSA_PTE_PPN_MASK) | \
-	(((ring) << 4) & Z_XTENSA_PTE_RING_MASK) | \
+	(((ring) << Z_XTENSA_PTE_RING_SHIFT) & Z_XTENSA_PTE_RING_MASK) | \
 	((attr) & Z_XTENSA_PTE_ATTR_MASK))
 
+#define Z_XTENSA_PTE_ATTR_GET(pte) \
+	(pte) & Z_XTENSA_PTE_ATTR_MASK
+
+#define Z_XTENSA_PTE_ATTR_SET(pte, attr) \
+	(((pte) & ~Z_XTENSA_PTE_ATTR_MASK) | (attr))
+
+#define Z_XTENSA_PTE_RING_SET(pte, ring) \
+	(((pte) & ~Z_XTENSA_PTE_RING_MASK) | \
+	((ring) << Z_XTENSA_PTE_RING_SHIFT))
+
+#define Z_XTENSA_PTE_RING_GET(pte) \
+	(((pte) & ~Z_XTENSA_PTE_RING_MASK) >> Z_XTENSA_PTE_RING_SHIFT)
+
+#define Z_XTENSA_PTE_ASID_GET(pte, rasid) \
+	(((rasid) >> ((((pte) & Z_XTENSA_PTE_RING_MASK) \
+		       >> Z_XTENSA_PTE_RING_SHIFT) * 8)) & 0xFF)
+
 #define Z_XTENSA_TLB_ENTRY(vaddr, way) \
 	(((vaddr) & Z_XTENSA_PTE_PPN_MASK) | (way))
 
@@ -38,11 +57,38 @@
 	 (((vaddr) >> Z_XTENSA_PPN_SHIFT) & 0x03U))
 
 #define Z_XTENSA_L2_POS(vaddr) \
-	(((vaddr) & Z_XTENSA_L2_MASK) >> Z_XTENSA_PPN_SHIFT)
+	(((vaddr) & Z_XTENSA_L2_MASK) >> 12U)
+
+#define Z_XTENSA_L1_POS(vaddr) \
+	((vaddr) >> 22U)
+
+/* PTE attributes for entries in the L1 page table.  Should never be
+ * writable, may be cached in non-SMP contexts only
+ */
+#if CONFIG_MP_MAX_NUM_CPUS == 1
+#define Z_XTENSA_PAGE_TABLE_ATTR Z_XTENSA_MMU_CACHED_WB
+#else
+#define Z_XTENSA_PAGE_TABLE_ATTR 0
+#endif
+
+/* This ASID is shared between all domains and kernel. */
+#define Z_XTENSA_MMU_SHARED_ASID 255
+
+/* Fixed data TLB way to map the page table */
+#define Z_XTENSA_MMU_PTE_WAY 7
+
+/* Fixed data TLB way to map the vecbase */
+#define Z_XTENSA_MMU_VECBASE_WAY 8
 
 /* Kernel specific ASID. Ring field in the PTE */
 #define Z_XTENSA_KERNEL_RING 0
 
+/* User specific ASID. Ring field in the PTE */
+#define Z_XTENSA_USER_RING 2
+
+/* Ring value for MMU_SHARED_ASID */
+#define Z_XTENSA_SHARED_RING 3
+
 /* Number of data TLB ways [0-9] */
 #define Z_XTENSA_DTLB_WAYS 10
 
@@ -96,6 +142,14 @@
 #define Z_XTENSA_PAGE_TABLE_VADDR \
 	Z_XTENSA_PTE_ENTRY_VADDR(Z_XTENSA_PTEVADDR)
 
+/*
+ * Get asid for a given ring from rasid register.
+ * rasid contains four asid, one per ring.
+ */
+
+#define Z_XTENSA_RASID_ASID_GET(rasid, ring) \
+	(((rasid) >> ((ring) * 8)) & 0xff)
+
 static ALWAYS_INLINE void xtensa_rasid_set(uint32_t rasid)
 {
 	__asm__ volatile("wsr %0, rasid\n\t"
@@ -110,6 +164,16 @@ static ALWAYS_INLINE uint32_t xtensa_rasid_get(void)
 	return rasid;
 }
 
+static ALWAYS_INLINE void xtensa_rasid_asid_set(uint8_t asid, uint8_t pos)
+{
+	uint32_t rasid = xtensa_rasid_get();
+
+	rasid = (rasid & ~(0xff << (pos * 8))) | ((uint32_t)asid << (pos * 8));
+
+	xtensa_rasid_set(rasid);
+}
+
+
 static ALWAYS_INLINE void xtensa_itlb_entry_invalidate(uint32_t entry)
 {
 	__asm__ volatile("iitlb %0\n\t"
@@ -201,6 +265,21 @@ static ALWAYS_INLINE void xtensa_ptevaddr_set(void *ptables)
 	__asm__ volatile("wsr.ptevaddr %0" : : "a"((uint32_t)ptables));
 }
 
+/**
+ * @brief Get the current page tables.
+ *
+ * The page tables is obtained by reading ptevaddr address.
+ *
+ * @return ptables The page tables address (virtual address)
+ */
+static ALWAYS_INLINE void *xtensa_ptevaddr_get(void)
+{
+	uint32_t ptables;
+
+	__asm__ volatile("rsr.ptevaddr %0" : "=a" (ptables));
+
+	return (void *)ptables;
+}
 /*
  * The following functions are helpful when debugging.
  */

arch/xtensa/core/offsets/offsets.c

@@ -5,6 +5,7 @@
 
 #include <gen_offset.h>
 #include <kernel_offsets.h>
+#include <zephyr/arch/xtensa/thread.h>
 
 #include <xtensa-asm2-context.h>
 
@@ -60,4 +61,10 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu14);
 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fpu15);
 #endif
 
+#ifdef CONFIG_USERSPACE
+GEN_OFFSET_SYM(_thread_arch_t, psp);
+GEN_OFFSET_SYM(_thread_arch_t, ptables);
+#endif
+
+
 GEN_ABS_SYM_END

arch/xtensa/core/syscall_helper.c

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2022 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/xtensa/syscall.h>
+
+uintptr_t arch_syscall_invoke6_helper(uintptr_t arg1, uintptr_t arg2,
+				      uintptr_t arg3, uintptr_t arg4,
+				      uintptr_t arg5, uintptr_t arg6,
+				      uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+	register uintptr_t a3 __asm__("%a3") = arg2;
+	register uintptr_t a4 __asm__("%a4") = arg3;
+	register uintptr_t a5 __asm__("%a5") = arg4;
+	register uintptr_t a8 __asm__("%a8") = arg5;
+	register uintptr_t a9 __asm__("%a9") = arg6;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
+			   "r" (a5), "r" (a8), "r" (a9)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke5_helper(uintptr_t arg1, uintptr_t arg2,
+				      uintptr_t arg3, uintptr_t arg4,
+				      uintptr_t arg5, uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+	register uintptr_t a3 __asm__("%a3") = arg2;
+	register uintptr_t a4 __asm__("%a4") = arg3;
+	register uintptr_t a5 __asm__("%a5") = arg4;
+	register uintptr_t a8 __asm__("%a8") = arg5;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
+			   "r" (a5), "r" (a8)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke4_helper(uintptr_t arg1, uintptr_t arg2,
+				      uintptr_t arg3, uintptr_t arg4,
+				      uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+	register uintptr_t a3 __asm__("%a3") = arg2;
+	register uintptr_t a4 __asm__("%a4") = arg3;
+	register uintptr_t a5 __asm__("%a5") = arg4;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
+			   "r" (a5)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke3_helper(uintptr_t arg1, uintptr_t arg2,
+				      uintptr_t arg3, uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+	register uintptr_t a3 __asm__("%a3") = arg2;
+	register uintptr_t a4 __asm__("%a4") = arg3;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke2_helper(uintptr_t arg1, uintptr_t arg2,
+				      uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+	register uintptr_t a3 __asm__("%a3") = arg2;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6), "r" (a3)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke1_helper(uintptr_t arg1, uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+	register uintptr_t a6 __asm__("%a6") = arg1;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2), "r" (a6)
+			 : "memory");
+
+	return a2;
+}
+
+uintptr_t arch_syscall_invoke0_helper(uintptr_t call_id)
+{
+	register uintptr_t a2 __asm__("%a2") = call_id;
+
+	__asm__ volatile("syscall\n\t"
+			 : "=r" (a2)
+			 : "r" (a2)
+			 : "memory");
+
+	return a2;
+}