dts: bindings: add pinctrl binding for nxp mcux rt1xxx

Add dts binding for rt1xxx pinctrl driver settings. A binding file is
present for the pinctrl node itself, and for the pinctrl child node that
defines all pinmux options

Signed-off-by: Hake Huang <[email protected]>
Signed-off-by: Daniel DeGrasse <[email protected]>

Author: hakehuang

dts/bindings/pinctrl/nxp,imx-iomuxc.yaml

@@ -0,0 +1,35 @@
+# Copyright (c) 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  This compatible binding should be applied to the device's iomuxc DTS node.
+  the DTS node will be populated with all pinmux options for the specific SOC.
+  These options can then be used in a pinctrl node with the "nxp,mcux-rt-pinctrl"
+  compatible string to define pin groups.
+
+  The user should not edit the bindings defined within this node to make pinmux
+  selections, but should instead edit the pinctrl groups for their board.
+
+compatible: "nxp,imx-iomuxc"
+
+include:
+    - name: base.yaml
+
+properties:
+    reg:
+      required: true
+
+child-binding:
+  description: MCUX RT pin mux option
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        An array of values defining the pin mux selection, in the following format:
+        <mux_register, mux_val, input_reg, daisy_val, cfg_reg>
+        mux_register: register that will be written to to make mux selection
+        mux_val: value to write to mux_register
+        input_reg: peripheral register that will direct peripheral signal to pin
+        daisy_val: value to write to input_reg
+        cfg_reg: register that will configure pin pull, drive strength, and open drain

dts/bindings/pinctrl/nxp,mcux-rt-pinctrl.yaml

@@ -0,0 +1,156 @@
+# Copyright (c) 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
+  nodes can be autogenerated using the MCUXpresso config tools combined with
+  the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
+  fields in a group select the pins to be configured, and the remaining
+  devicetree properties set configuration values for those pins
+  for example, here is an group configuring LPUART1 pins:
+
+  group0 {
+    pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx,
+      &iomuxc_gpio_ad_b0_13_lpuart1_rx>;
+    drive-strength = "r0-6";
+    slew-rate = "slow";
+    nxp,speed = "100-mhz";
+  };
+
+  Note that the mux, mode, input, daisy, and cfg values must be aligned for
+  correct configuration
+  This will select GPIO_AD_B0_12 as LPUART1 TX, and GPIO_AD_B0_13 as LPUART1 RX.
+  Both pins will be configured with a weak latch, drive strength of "r0-6",
+  slow slew rate, and 100 MHZ speed.
+  Note that the soc level iomuxc dts file can be examined to find the possible
+  pinmux options. Here are the affects of each property on the
+  IOMUXC SW_PAD_CTL register:
+  input-schmitt-enable: HYS=1
+  drive-open-drain: ODE=1
+  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
+  bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
+  bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
+  bias-disable: PKE=0
+  slew-rate: SRE=<enum_idx>
+  drive-strength: DSE=<enum_idx>
+  nxp,speed: SPEED=<enum_idx>
+
+  If only required properties are supplied, the pin will have the following
+  configuration:
+  HYS=0,
+  ODE=0,
+  SION=0,
+  PUE=0,
+  PUS=0,
+  PKE=1,
+  SRE=<slew-rate>,
+  DSE=<drive-strength>,
+  SPEED=<nxp,speed>
+
+
+compatible: "nxp,mcux-rt-pinctrl"
+
+include:
+    - name: base.yaml
+    - name: pincfg-node-group.yaml
+      child-binding:
+        child-binding:
+          property-allowlist:
+            - input-schmitt-enable
+            - drive-open-drain
+            - input-enable
+            - bias-disable
+            - bias-pull-down
+            - bias-pull-up
+
+child-binding:
+  description: MCUX RT pin controller pin group
+  child-binding:
+    description: |
+      MCUX RT pin controller pin configuration node.
+    properties:
+      pinmux:
+        required: true
+        type: phandles
+        description: |
+          Pin mux selections for this group. See the soc level iomuxc DTSI file
+          for a defined list of these options.
+      drive-strength:
+        required: true
+        type: string
+        enum:
+          - "disabled"
+          - "r0"
+          - "r0-2"
+          - "r0-3"
+          - "r0-4"
+          - "r0-5"
+          - "r0-6"
+          - "r0-7"
+        description: |
+          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
+          the drive strength is expressed as a output impedance at a given voltage,
+          but maximum current values can be calculated from these impedances
+          for a specific load impedance.
+          000 DSE_0_output_driver_disabled_ — output driver disabled
+          001 DSE_1_R0_1 — 157 Ohm impedance @3.3V, 260 Ohm impedance @1.8V
+          010 DSE_2_R0_2 — 78 Ohm @3.3V, 130 Ohm @1.8V
+          011 DSE_3_R0_3 — 53 Ohm @3.3V, 88 Ohm @1.8V
+          100 DSE_4_R0_4 — 39 Ohm @3.3V, 65 Ohm @1.8V
+          101 DSE_5_R0_5 — 32 Ohm @3.3V, 52 Ohm @1.8V
+          110 DSE_6_R0_6 — 32 Ohm @3.3V, 43 Ohm @1.8V
+          111 DSE_7_R0_7 — 26 Ohm @3.3V, 37 Ohm @1.8V
+      bias-pull-up-value:
+        required: false
+        type: string
+        default: "47k"
+        enum:
+          - "unused"
+          - "47k"
+          - "100k"
+          - "22k"
+        description: |
+          Select the value of the pull up resistor present on this pin
+          Corresponds to the PUS field in the IOMUXC peripheral.
+          47k resistor selected as default due to this being the default pullup
+          value on most SOC pins
+          00 Unused- no change will be applied to pin
+          01 PUS_1_47K_Ohm_Pull_Up — 47K Ohm Pull Up
+          10 PUS_2_100K_Ohm_Pull_Up — 100K Ohm Pull Up
+          11 PUS_2_22K_Ohm_Pull_Up — 22K Ohm Pull Up
+
+      bias-pull-down-value:
+        required: false
+        type: string
+        default: "100k"
+        enum:
+          - "100k"
+        description: |
+          Select the value of the pull up resistor present on this pin
+          Corresponds to the PUS field in the IOMUXC peripheral. 100k is
+          currently the only supported pull down resistance.
+          00 PUS_0_100K_Ohm_Pull_Down - 100K Ohm Pull Down
+      slew-rate:
+        required: true
+        type: string
+        enum:
+          - "slow"
+          - "fast"
+        description: |
+          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
+          0 SRE_0_Slow_Slew_Rate — Slow Slew Rate
+          1 SRE_1_Fast_Slew_Rate — Fast Slew Rate
+      nxp,speed:
+        required: false
+        type: string
+        enum:
+          - "50-mhz"
+          - "100-mhz"
+          - "150-mhz"
+          - "200-mhz"
+        description: |
+          Sets pin speed. Corresponds to SPEED field in IOMUXC peripheral
+          00 SPEED_0_low_50MHz_ — low(50MHz)
+          01 SPEED_1_medium_100MHz_ — medium(100MHz)
+          10 SPEED_2_medium_150MHz_ — medium(150MHz)
+          11 SPEED_3_max_200MHz_ — max(200MHz)