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FelixWang47831MaureenHelm
FelixWang47831
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MaureenHelm
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drivers: Counter: LPIT Support on Zephyr
1.Add dts bindings nxp,lpit-channel.yaml and nxp,lpit.yaml 2.Provide counter driver based on lpit driver from NXP mcux-sdk-ng Signed-off-by: Felix Wang <[email protected]>
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‎drivers/counter/CMakeLists.txt

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@@ -33,6 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_SNVS counter_mcux_snv
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_TPM counter_mcux_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_XEC counter_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPTMR counter_mcux_lptmr.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPIT counter_mcux_lpit.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MAXIM_DS3231 maxim_ds3231.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_NATIVE_SIM counter_native_sim.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE counter_handlers.c)

‎drivers/counter/Kconfig

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@@ -70,6 +70,8 @@ source "drivers/counter/Kconfig.xec"
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source "drivers/counter/Kconfig.mcux_lptmr"
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source "drivers/counter/Kconfig.mcux_lpit"
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source "drivers/counter/Kconfig.maxim_ds3231"
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source "drivers/counter/Kconfig.native_sim"

‎drivers/counter/Kconfig.mcux_lpit

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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# MCUXpresso SDK Low Power Periodic Interrupt Timer (LPIT)
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config COUNTER_MCUX_LPIT
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bool "NXP LPIT driver"
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default y
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depends on DT_HAS_NXP_LPIT_CHANNEL_ENABLED && \
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DT_HAS_NXP_LPIT_ENABLED
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help
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Enable support for the NXP Low Power Periodic Interrupt Timer (LPIT).

‎drivers/counter/counter_mcux_lpit.c

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/*
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* Copyright 2023, 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpit
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/irq.h>
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#include <fsl_lpit.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(counter_lpit, CONFIG_COUNTER_LOG_LEVEL);
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/* Device holds a pointer to pointer to data */
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#define LPIT_CHANNEL_DATA(dev) (*(struct mcux_lpit_channel_data *const *const)dev->data)
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/* dev->config->data is an array of data pointers ordered by channel number,
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* dev->data is a pointer to one of these pointers in that array,
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* so the value of the dev->data - dev->config->data is the channel index
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*/
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#define LPIT_CHANNEL_ID(dev) \
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(((struct mcux_lpit_channel_data *const *)dev->data) - \
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((const struct mcux_lpit_config *)dev->config)->data)
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struct mcux_lpit_channel_data {
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uint32_t top; /* Top value of the counter */
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counter_top_callback_t top_callback; /* Callback when counter turns around */
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void *top_user_data; /* User data for top callback */
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};
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struct mcux_lpit_config {
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struct counter_config_info info;
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LPIT_Type *base; /* Poniter to LPIT peripheral instance base address*/
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lpit_config_t lpit_config; /* LPIT configuration structure */
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int num_channels; /* Number of channels for one LPIT instance*/
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void (*irq_config_func)(const struct device *dev);
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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/* Point to array of channels data for this LPIT instance */
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struct mcux_lpit_channel_data *const *data;
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/* Point to array of channel devices for this LPIT instance */
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const struct device *const *channels;
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};
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static uint32_t mcux_lpit_get_top_value(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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/*
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* The underlying HAL driver function LPIT_SetTimerPeriod()
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* automatically subtracted 1 from the value that ends up in
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* TVAL so for reporting purposes we need to add it back in
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* here to by consistent.
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*/
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return (config->base->CHANNEL[channel_id].TVAL + 1U);
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}
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static int mcux_lpit_start(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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LOG_DBG("period is %d", mcux_lpit_get_top_value(dev));
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LPIT_EnableInterrupts(config->base, (1U << channel_id));
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LPIT_StartTimer(config->base, channel_id);
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return 0;
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}
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static int mcux_lpit_stop(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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LPIT_DisableInterrupts(config->base, channel_id);
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LPIT_StopTimer(config->base, channel_id);
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return 0;
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}
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static int mcux_lpit_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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*ticks = LPIT_GetCurrentTimerCount(config->base, channel_id);
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return 0;
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}
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static int mcux_lpit_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
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{
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const struct mcux_lpit_config *config = dev->config;
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struct mcux_lpit_channel_data *data = LPIT_CHANNEL_DATA(dev);
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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/* Note: The underlying HAL driver function LPIT_SetTimerPeriod() assert(ticks > 2U) */
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if (cfg->ticks < 2U || cfg->ticks > config->info.max_top_value) {
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return -EINVAL;
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}
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data->top_callback = cfg->callback;
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data->top_user_data = cfg->user_data;
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if ((config->base->CHANNEL[channel_id].TCTRL & LPIT_TCTRL_T_EN_MASK) != 0) {
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/* Timer already enabled, check flags before resetting */
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if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) != 0) {
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return -ENOTSUP;
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}
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mcux_lpit_stop(dev);
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LPIT_SetTimerPeriod(config->base, channel_id, cfg->ticks);
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mcux_lpit_start(dev);
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} else {
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LPIT_SetTimerPeriod(config->base, channel_id, cfg->ticks);
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}
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return 0;
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}
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static uint32_t mcux_lpit_get_pending_int(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint8_t channel_id = LPIT_CHANNEL_ID(dev);
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return (LPIT_GetStatusFlags(config->base) >> channel_id) & 0x1U;
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}
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static uint32_t mcux_lpit_get_frequency(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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uint32_t clock_rate;
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if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) {
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LOG_ERR("Failed to get clock rate");
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return 0;
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}
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return clock_rate;
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}
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static void mcux_lpit_isr(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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LOG_DBG("lpit counter isr");
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uint32_t flags = LPIT_GetStatusFlags(config->base);
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for (int channel_index = 0; channel_index < config->num_channels; channel_index++) {
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if ((flags & (1U << channel_index)) == 0) {
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continue;
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}
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/* Clear interrupt flag */
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LPIT_ClearStatusFlags(config->base, (1U << channel_index));
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struct mcux_lpit_channel_data *data =
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LPIT_CHANNEL_DATA(config->channels[channel_index]);
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if (data->top_callback != NULL) {
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data->top_callback(dev, data->top_user_data);
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}
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}
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}
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static int mcux_lpit_init(const struct device *dev)
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{
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const struct mcux_lpit_config *config = dev->config;
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lpit_config_t lpit_config;
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uint32_t clock_rate;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("Clock control device not ready");
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return -ENODEV;
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}
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LPIT_GetDefaultConfig(&lpit_config);
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lpit_config.enableRunInDebug = config->lpit_config.enableRunInDebug;
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lpit_config.enableRunInDoze = config->lpit_config.enableRunInDoze;
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LPIT_Init(config->base, &lpit_config);
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clock_rate = mcux_lpit_get_frequency(dev);
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config->irq_config_func(dev);
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for (int channel_index = 0U; channel_index < config->num_channels; channel_index++) {
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LPIT_SetTimerPeriod(config->base, channel_index, config->info.max_top_value);
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}
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return 0;
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}
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static DEVICE_API(counter, mcux_lpit_driver_api) = {
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.start = mcux_lpit_start,
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.stop = mcux_lpit_stop,
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.get_value = mcux_lpit_get_value,
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.set_top_value = mcux_lpit_set_top_value,
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.get_pending_int = mcux_lpit_get_pending_int,
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.get_top_value = mcux_lpit_get_top_value,
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.get_freq = mcux_lpit_get_frequency,
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};
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/* Creates a device for a channel (needed for counter API) */
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#define MCUX_LPIT_CHANNEL_DEV_INIT(node, lpit_inst) \
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DEVICE_DT_DEFINE(node, NULL, NULL, \
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(void *)&mcux_lpit_##lpit_inst##_channel_datas[DT_REG_ADDR(node)], \
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&mcux_lpit_##lpit_inst##_config, POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, &mcux_lpit_driver_api);
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/* Creates a decleration for each lpit channel */
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#define MCUX_LPIT_CHANNEL_DECLARATIONS(node) \
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static struct mcux_lpit_channel_data mcux_lpit_channel_data_##node;
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/* Initializes an element of the channel data pointer array */
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#define MCUX_LPIT_INSERT_CHANNEL_INTO_ARRAY(node) \
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[DT_REG_ADDR(node)] = &mcux_lpit_channel_data_##node,
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#define MCUX_LPIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY(node) [DT_REG_ADDR(node)] = DEVICE_DT_GET(node),
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#define MCUX_LPIT_IRQ_CONFIG_DECLARATIONS(n) \
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static void mcux_lpit_irq_config_func_##n(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, 0, irq), DT_INST_IRQ_BY_IDX(n, 0, priority), \
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mcux_lpit_isr, DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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};
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#define MCUX_LPIT_SETUP_IRQ_CONFIG(n) MCUX_LPIT_IRQ_CONFIG_DECLARATIONS(n);
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#define MCUX_LPIT_SETUP_IRQ_ARRAY(ignored)
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#define COUNTER_MCUX_LPIT_DEVICE_INIT(n) \
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\
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/* Setup the IRQ either for parent irq or per channel irq */ \
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MCUX_LPIT_SETUP_IRQ_CONFIG(n) \
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\
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/* Create channel declarations */ \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, MCUX_LPIT_CHANNEL_DECLARATIONS) \
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\
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/* Array of channel devices */ \
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static struct mcux_lpit_channel_data \
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*const mcux_lpit_##n##_channel_datas[DT_INST_FOREACH_CHILD_SEP_VARGS( \
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n, DT_NODE_HAS_COMPAT, (+), nxp_lpit_channel)] = { \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, \
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MCUX_LPIT_INSERT_CHANNEL_INTO_ARRAY)}; \
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\
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/* forward declaration */ \
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static const struct mcux_lpit_config mcux_lpit_##n##_config; \
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\
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/* Create all the channel/counter devices */ \
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DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, MCUX_LPIT_CHANNEL_DEV_INIT, n) \
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\
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/* This channel device array is needed by the module device ISR */ \
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const struct device *const mcux_lpit_##n##_channels[DT_INST_FOREACH_CHILD_SEP_VARGS( \
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n, DT_NODE_HAS_COMPAT, (+), nxp_lpit_channel)] = { \
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DT_INST_FOREACH_CHILD_STATUS_OKAY(n, MCUX_LPIT_INSERT_CHANNEL_DEVICE_INTO_ARRAY)}; \
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\
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MCUX_LPIT_SETUP_IRQ_ARRAY(n) \
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\
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/* This config struct is shared by all the channels and parent device */ \
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static const struct mcux_lpit_config mcux_lpit_##n##_config = { \
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.info = \
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{ \
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.max_top_value = DT_INST_PROP(n, max_load_value), \
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.channels = 0U, \
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}, \
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.base = (LPIT_Type *)DT_INST_REG_ADDR(n), \
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.lpit_config = \
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{ \
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.enableRunInDebug = DT_INST_PROP(n, enable_run_in_debug), \
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.enableRunInDoze = DT_INST_PROP(n, enable_run_in_doze), \
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}, \
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.irq_config_func = mcux_lpit_irq_config_func_##n, \
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.num_channels = DT_INST_FOREACH_CHILD_SEP_VARGS(n, DT_NODE_HAS_COMPAT, (+), \
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nxp_lpit_channel), \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name), \
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.data = mcux_lpit_##n##_channel_datas, \
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.channels = mcux_lpit_##n##_channels, \
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}; \
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\
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/* Init parent device in order to handle ISR and init. */ \
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DEVICE_DT_INST_DEFINE(n, &mcux_lpit_init, NULL, NULL, &mcux_lpit_##n##_config, \
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POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, NULL);
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DT_INST_FOREACH_STATUS_OKAY(COUNTER_MCUX_LPIT_DEVICE_INIT)

‎dts/bindings/counter/nxp,lpit-channel.yaml

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# Copyright 2025 NXP
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# SPDX-License-Identifier Apache-2.0
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description: |
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Child node for the Low Power Periodic Interrupt Timer node, intended
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for an individual timer channel
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compatible: "nxp,lpit-channel"
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include: base.yaml
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properties:
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reg:
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required: true

‎dts/bindings/counter/nxp,lpit.yaml

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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP Low Power Periodic Interrupt Timer (LPIT)
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compatible: "nxp,lpit"
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include: base.yaml
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properties:
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reg:
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required: true
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clocks:
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required: true
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max-load-value:
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type: int
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required: true
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description: Maximum timeout ticks allowed for timer channels.
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enable-run-in-debug:
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type: boolean
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description: Set 1 to allows timer channels to continue running when the chip enters Debug mode.
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enable-run-in-doze:
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type: boolean
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description: Set 1 to allows timer channels to continue running when the chip enters Doze mode.

‎modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

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@@ -89,6 +89,7 @@ set_variable_ifdef(CONFIG_WDT_MCUX_WDOG CONFIG_MCUX_COMPONENT_driver.wdo
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set_variable_ifdef(CONFIG_WDT_MCUX_WDOG32 CONFIG_MCUX_COMPONENT_driver.wdog32)
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set_variable_ifdef(CONFIG_COUNTER_MCUX_GPT CONFIG_MCUX_COMPONENT_driver.gpt)
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set_variable_ifdef(CONFIG_MCUX_GPT_TIMER CONFIG_MCUX_COMPONENT_driver.gpt)
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set_variable_ifdef(CONFIG_COUNTER_MCUX_LPIT CONFIG_MCUX_COMPONENT_driver.lpit)
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set_variable_ifdef(CONFIG_DISPLAY_MCUX_ELCDIF CONFIG_MCUX_COMPONENT_driver.elcdif)
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set_variable_ifdef(CONFIG_MCUX_PXP CONFIG_MCUX_COMPONENT_driver.pxp)
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set_variable_ifdef(CONFIG_LV_USE_GPU_NXP_PXP CONFIG_MCUX_COMPONENT_driver.pxp)

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