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mrjimenezmrjimenez
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drivers: ethernet: Run clang-format before applying a patch
This patch just formats the file before the real patch, otherwise the changes would be hard to read. The only addition was a third parameter (NULL) to all the usages of the macro WAIT_FOR, since the dangling comma triggered conflicts between clang-format and check_compliance.py. Signed-off-by: Marcelo Roberto Jimenez <[email protected]>
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+46
-48
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-48
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‎drivers/ethernet/eth_xmc4xxx.c‎

Lines changed: 46 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -43,14 +43,20 @@ LOG_MODULE_REGISTER(eth_xmc4xxx);
4343
#define INFINEON_OUI_B1 0x03
4444
#define INFINEON_OUI_B2 0x19
4545

46-
#define MODULO_INC_TX(val) {(val) = (++(val) < NUM_TX_DMA_DESCRIPTORS) ? (val) : 0; }
47-
#define MODULO_INC_RX(val) {(val) = (++(val) < NUM_RX_DMA_DESCRIPTORS) ? (val) : 0; }
46+
#define MODULO_INC_TX(val) \
47+
{ \
48+
(val) = (++(val) < NUM_TX_DMA_DESCRIPTORS) ? (val) : 0; \
49+
}
50+
#define MODULO_INC_RX(val) \
51+
{ \
52+
(val) = (++(val) < NUM_RX_DMA_DESCRIPTORS) ? (val) : 0; \
53+
}
4854

4955
#define IS_OWNED_BY_DMA_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_OWN) != 0)
5056
#define IS_OWNED_BY_DMA_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_OWN) != 0)
5157

5258
#define IS_START_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_FS) != 0)
53-
#define IS_END_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_LS) != 0)
59+
#define IS_END_OF_FRAME_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_LS) != 0)
5460

5561
#define IS_TIMESTAMP_AVAILABLE_RX(desc) (((desc)->status & ETH_MAC_DMA_RDES0_TSA) != 0)
5662
#define IS_TIMESTAMP_AVAILABLE_TX(desc) (((desc)->status & ETH_MAC_DMA_TDES0_TTSS) != 0)
@@ -69,23 +75,23 @@ LOG_MODULE_REGISTER(eth_xmc4xxx);
6975
XMC_ETH_MAC_EVENT_RECEIVE | XMC_ETH_MAC_EVENT_TRANSMIT | ETH_INTERRUPT_ENABLE_NIE_Msk | \
7076
ETH_INTERRUPT_ENABLE_AIE_Msk)
7177

72-
#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK 0x03ffffffu
73-
#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK 0x3fff3fffu
78+
#define ETH_MAC_DISABLE_MMC_INTERRUPT_MSK 0x03ffffffu
79+
#define ETH_MAC_DISABLE_MMC_IPC_RECEIVE_INTERRUPT_MSK 0x3fff3fffu
7480

7581
#define ETH_STATUS_CLEARABLE_BITS 0x1e7ffu
7682

7783
#define ETH_RX_DMA_DESC_SECOND_ADDR_CHAINED_MASK BIT(14)
7884

79-
#define ETH_RESET_TIMEOUT_USEC 200000u
85+
#define ETH_RESET_TIMEOUT_USEC 200000u
8086
#define ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC 100000u
8187

82-
#define ETH_LINK_SPEED_10M 0
88+
#define ETH_LINK_SPEED_10M 0
8389
#define ETH_LINK_SPEED_100M 1
8490

8591
#define ETH_LINK_DUPLEX_HALF 0
8692
#define ETH_LINK_DUPLEX_FULL 1
8793

88-
#define ETH_PTP_CLOCK_FREQUENCY 50000000
94+
#define ETH_PTP_CLOCK_FREQUENCY 50000000
8995
#define ETH_PTP_RATE_ADJUST_RATIO_MIN 0.9
9096
#define ETH_PTP_RATE_ADJUST_RATIO_MAX 1.1
9197

@@ -467,7 +473,6 @@ static struct net_pkt *eth_xmc4xxx_rx_pkt(const struct device *dev)
467473
dma_desc = &rx_dma_desc[tail];
468474
}
469475

470-
471476
MODULO_INC_RX(tail);
472477
dev_data->dma_desc_rx_tail = tail;
473478

@@ -605,12 +610,10 @@ static inline void eth_xmc4xxx_set_link(ETH_GLOBAL_TypeDef *regs, struct phy_lin
605610

606611
reg &= ~(ETH_MAC_CONFIGURATION_DM_Msk | ETH_MAC_CONFIGURATION_FES_Msk);
607612

608-
val = PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_LINK_DUPLEX_FULL :
609-
ETH_LINK_DUPLEX_HALF;
613+
val = PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_LINK_DUPLEX_FULL : ETH_LINK_DUPLEX_HALF;
610614
reg |= FIELD_PREP(ETH_MAC_CONFIGURATION_DM_Msk, val);
611615

612-
val = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_LINK_SPEED_100M :
613-
ETH_LINK_SPEED_10M;
616+
val = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_10M;
614617
reg |= FIELD_PREP(ETH_MAC_CONFIGURATION_FES_Msk, val);
615618

616619
regs->MAC_CONFIGURATION = reg;
@@ -708,8 +711,8 @@ static int eth_xmc4xxx_rx_dma_descriptors_init(const struct device *dev)
708711

709712
for (int i = 0; i < NUM_RX_DMA_DESCRIPTORS; i++) {
710713
XMC_ETH_MAC_DMA_DESC_t *dma_desc = &rx_dma_desc[i];
711-
struct net_buf *rx_buf = net_pkt_get_reserve_rx_data(CONFIG_NET_BUF_DATA_SIZE,
712-
K_NO_WAIT);
714+
struct net_buf *rx_buf =
715+
net_pkt_get_reserve_rx_data(CONFIG_NET_BUF_DATA_SIZE, K_NO_WAIT);
713716

714717
if (rx_buf == NULL) {
715718
eth_xmc4xxx_free_rx_bufs(dev);
@@ -733,8 +736,8 @@ static inline int eth_xmc4xxx_reset(const struct device *dev)
733736
dev_cfg->regs->BUS_MODE |= ETH_BUS_MODE_SWR_Msk;
734737

735738
/* reset may fail if the clocks are not properly setup */
736-
if (!WAIT_FOR((dev_cfg->regs->BUS_MODE & ETH_BUS_MODE_SWR_Msk) == 0,
737-
ETH_RESET_TIMEOUT_USEC,)) {
739+
if (!WAIT_FOR((dev_cfg->regs->BUS_MODE & ETH_BUS_MODE_SWR_Msk) == 0, ETH_RESET_TIMEOUT_USEC,
740+
NULL)) {
738741
return -ETIMEDOUT;
739742
}
740743

@@ -763,14 +766,14 @@ static inline void eth_xmc4xxx_mask_unused_interrupts(ETH_GLOBAL_TypeDef *regs)
763766
static inline int eth_xmc4xxx_init_timestamp_control_reg(ETH_GLOBAL_TypeDef *regs)
764767
{
765768
#if defined(CONFIG_NET_GPTP)
766-
regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk |
767-
ETH_TIMESTAMP_CONTROL_TSENALL_Msk;
769+
regs->TIMESTAMP_CONTROL =
770+
ETH_TIMESTAMP_CONTROL_TSENA_Msk | ETH_TIMESTAMP_CONTROL_TSENALL_Msk;
768771
#endif
769772

770773
#if defined(CONFIG_PTP_CLOCK_XMC4XXX)
771774
/* use fine control */
772-
regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk |
773-
ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk;
775+
regs->TIMESTAMP_CONTROL |=
776+
ETH_TIMESTAMP_CONTROL_TSCFUPDT_Msk | ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk;
774777

775778
/* make ptp run at 50MHz - implies 20ns increment for each increment of the */
776779
/* sub_second_register */
@@ -780,20 +783,20 @@ static inline int eth_xmc4xxx_init_timestamp_control_reg(ETH_GLOBAL_TypeDef *reg
780783
/* Therefore, K = ceil(f_out * 2^32 / f_cpu) */
781784

782785
uint32_t f_cpu = XMC_SCU_CLOCK_GetSystemClockFrequency();
783-
uint32_t K = (BIT64(32) * ETH_PTP_CLOCK_FREQUENCY + f_cpu / 2) / f_cpu;
786+
uint32_t K = (BIT64(32) * ETH_PTP_CLOCK_FREQUENCY + f_cpu / 2) / f_cpu;
784787

785788
regs->TIMESTAMP_ADDEND = K;
786789

787790
/* Addend register update */
788791
regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
789792
if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,
790-
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
793+
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
791794
return -ETIMEDOUT;
792795
}
793796

794797
regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
795798
if (!WAIT_FOR((regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,
796-
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
799+
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
797800
return -ETIMEDOUT;
798801
}
799802
#endif
@@ -808,8 +811,7 @@ static int eth_xmc4xxx_init(const struct device *dev)
808811
int ret;
809812

810813
sys_slist_init(&dev_data->tx_frame_list);
811-
k_sem_init(&dev_data->tx_desc_sem, NUM_TX_DMA_DESCRIPTORS,
812-
NUM_TX_DMA_DESCRIPTORS);
814+
k_sem_init(&dev_data->tx_desc_sem, NUM_TX_DMA_DESCRIPTORS, NUM_TX_DMA_DESCRIPTORS);
813815

814816
if (!device_is_ready(dev_cfg->phy_dev)) {
815817
LOG_ERR("Phy device not ready");
@@ -842,7 +844,6 @@ static int eth_xmc4xxx_init(const struct device *dev)
842844
/* disable jumbo frames */
843845
dev_cfg->regs->MAC_CONFIGURATION &= ~ETH_MAC_CONFIGURATION_JE_Msk;
844846

845-
846847
/* Initialize Filter registers - disable zero quanta pause*/
847848
dev_cfg->regs->FLOW_CONTROL = ETH_FLOW_CONTROL_DZPQ_Msk;
848849

@@ -893,8 +894,8 @@ static int eth_xmc4xxx_init(const struct device *dev)
893894
static enum ethernet_hw_caps eth_xmc4xxx_capabilities(const struct device *dev)
894895
{
895896
ARG_UNUSED(dev);
896-
enum ethernet_hw_caps caps = ETHERNET_LINK_10BASE | ETHERNET_LINK_100BASE |
897-
ETHERNET_HW_TX_CHKSUM_OFFLOAD | ETHERNET_HW_RX_CHKSUM_OFFLOAD;
897+
enum ethernet_hw_caps caps = ETHERNET_LINK_10BASE | ETHERNET_LINK_100BASE |
898+
ETHERNET_HW_TX_CHKSUM_OFFLOAD | ETHERNET_HW_RX_CHKSUM_OFFLOAD;
898899

899900
#if defined(CONFIG_PTP_CLOCK_XMC4XXX)
900901
caps |= ETHERNET_PTP;
@@ -947,7 +948,6 @@ static const struct device *eth_xmc4xxx_get_ptp_clock(const struct device *dev)
947948
}
948949
#endif
949950

950-
951951
#if defined(CONFIG_ETH_XMC4XXX_VLAN_HW_FILTER)
952952
int eth_xmc4xxx_vlan_setup(const struct device *dev, struct net_if *iface, uint16_t tag,
953953
bool enable)
@@ -959,8 +959,7 @@ int eth_xmc4xxx_vlan_setup(const struct device *dev, struct net_if *iface, uint1
959959

960960
if (enable) {
961961
dev_cfg->regs->VLAN_TAG = FIELD_PREP(ETH_VLAN_TAG_VL_Msk, tag) |
962-
ETH_VLAN_TAG_ETV_Msk |
963-
ETH_VLAN_TAG_ESVL_Msk;
962+
ETH_VLAN_TAG_ETV_Msk | ETH_VLAN_TAG_ESVL_Msk;
964963
dev_cfg->regs->MAC_FRAME_FILTER |= ETH_MAC_FRAME_FILTER_VTFE_Msk;
965964
} else {
966965
dev_cfg->regs->VLAN_TAG = 0;
@@ -996,19 +995,18 @@ static struct eth_xmc4xxx_config eth_xmc4xxx_config = {
996995
.phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle)),
997996
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
998997
.port_ctrl = {
999-
.rxd0 = DT_INST_ENUM_IDX(0, rxd0_port_ctrl),
1000-
.rxd1 = DT_INST_ENUM_IDX(0, rxd1_port_ctrl),
1001-
.rxd2 = DT_INST_ENUM_IDX_OR(0, rxd2_port_ctrl, 0),
1002-
.rxd3 = DT_INST_ENUM_IDX_OR(0, rxd3_port_ctrl, 0),
1003-
.clk_rmii = DT_INST_ENUM_IDX(0, rmii_rx_clk_port_ctrl),
1004-
.crs_dv = DT_INST_ENUM_IDX(0, crs_rx_dv_port_ctrl),
1005-
.crs = DT_INST_ENUM_IDX_OR(0, crs_port_ctrl, 0),
1006-
.rxer = DT_INST_ENUM_IDX(0, rxer_port_ctrl),
1007-
.col = DT_INST_ENUM_IDX_OR(0, col_port_ctrl, 0),
1008-
.clk_tx = DT_INST_ENUM_IDX_OR(0, tx_clk_port_ctrl, 0),
1009-
.mode = DT_INST_ENUM_IDX_OR(0, phy_connection_type, 0),
1010-
}
1011-
};
998+
.rxd0 = DT_INST_ENUM_IDX(0, rxd0_port_ctrl),
999+
.rxd1 = DT_INST_ENUM_IDX(0, rxd1_port_ctrl),
1000+
.rxd2 = DT_INST_ENUM_IDX_OR(0, rxd2_port_ctrl, 0),
1001+
.rxd3 = DT_INST_ENUM_IDX_OR(0, rxd3_port_ctrl, 0),
1002+
.clk_rmii = DT_INST_ENUM_IDX(0, rmii_rx_clk_port_ctrl),
1003+
.crs_dv = DT_INST_ENUM_IDX(0, crs_rx_dv_port_ctrl),
1004+
.crs = DT_INST_ENUM_IDX_OR(0, crs_port_ctrl, 0),
1005+
.rxer = DT_INST_ENUM_IDX(0, rxer_port_ctrl),
1006+
.col = DT_INST_ENUM_IDX_OR(0, col_port_ctrl, 0),
1007+
.clk_tx = DT_INST_ENUM_IDX_OR(0, tx_clk_port_ctrl, 0),
1008+
.mode = DT_INST_ENUM_IDX_OR(0, phy_connection_type, 0),
1009+
}};
10121010

10131011
static struct eth_xmc4xxx_data eth_xmc4xxx_data = {
10141012
.mac_addr = DT_INST_PROP_OR(0, local_mac_address, {0}),
@@ -1035,7 +1033,7 @@ static int eth_xmc4xxx_ptp_clock_set(const struct device *dev, struct net_ptp_ti
10351033

10361034
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSINIT_Msk;
10371035
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSINIT_Msk) == 0,
1038-
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
1036+
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
10391037
return -ETIMEDOUT;
10401038
}
10411039

@@ -1088,7 +1086,7 @@ static int eth_xmc4xxx_ptp_clock_adjust(const struct device *dev, int increment)
10881086

10891087
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSUPDT_Msk;
10901088
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSUPDT_Msk) == 0,
1091-
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
1089+
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
10921090
return -ETIMEDOUT;
10931091
}
10941092

@@ -1116,7 +1114,7 @@ static int eth_xmc4xxx_ptp_clock_rate_adjust(const struct device *dev, double ra
11161114
/* Addend register update */
11171115
dev_cfg->regs->TIMESTAMP_CONTROL |= ETH_TIMESTAMP_CONTROL_TSADDREG_Msk;
11181116
if (!WAIT_FOR((dev_cfg->regs->TIMESTAMP_CONTROL & ETH_TIMESTAMP_CONTROL_TSADDREG_Msk) == 0,
1119-
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC,)) {
1117+
ETH_TIMESTAMP_CONTROL_REG_TIMEOUT_USEC, NULL)) {
11201118
return -ETIMEDOUT;
11211119
}
11221120

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