dts: arm: rcar_gen3_cr7: Add I2C support to DTS

Add I2C bus initial support to Renesas R-Car SoC series.
Both I2C2 & I2C4 buses are supported on R-Car H3 board.

Signed-off-by: Aymeric Aillet <[email protected]>

Author: aaillet

boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts

@@ -57,3 +57,11 @@
 &scif1 {
 	status = "okay";
 };
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};

dts/arm/renesas/gen3/rcar_gen3_cr7.dtsi

@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/renesas_rcar_cpg.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
 
 / {
 	cpus {
@@ -104,6 +105,34 @@
 			label = "can0";
 		};
 
+		i2c2: i2c@e6510000 {
+			compatible = "renesas,rcar-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe6510000 0x40>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 929>;
+			status = "disabled";
+			label = "i2c2";
+		};
+
+		i2c4: i2c@e66d8000 {
+			compatible = "renesas,rcar-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0xe66d8000 0x40>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 927>;
+			status = "disabled";
+			label = "i2c4";
+		};
+
 		scif1: serial@e6e68000 {
 			compatible = "renesas,rcar-scif";
 			reg = <0xe6e68000 0x64>;