arch: arm: Add Cortex-R support

This adds initial Cortex-R support for interrupts and context switching.

Signed-off-by: Bradley Bolen <[email protected]>

Author: Bradley Bolen

arch/arm/core/CMakeLists.txt

@@ -25,3 +25,5 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M cortex_m)
 add_subdirectory_ifdef(CONFIG_ARM_CORE_MPU  cortex_m/mpu)
 add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M_HAS_CMSE cortex_m/cmse)
+
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_r)

arch/arm/core/Kconfig

@@ -26,6 +26,66 @@ config CPU_CORTEX_M
 	help
 	  This option signifies the use of a CPU of the Cortex-M family.
 
+config CPU_CORTEX_R
+	bool
+	select CPU_CORTEX
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select HAS_FLASH_LOAD_OFFSET
+	select HAS_DTS
+	select ARCH_HAS_STACK_PROTECTION if ARM_CORE_MPU
+	select ARCH_HAS_USERSPACE if ARM_CORE_MPU
+	help
+	  This option signifies the use of a CPU of the Cortex-R family.
+
+config ISA_THUMB2
+	bool
+	help
+	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
+
+	  Thumb-2 technology is the instruction set underlying the ARM Cortex
+	  architecture which provides enhanced levels of performance, energy
+	  efficiency, and code density for a wide range of embedded
+	  applications.
+
+	  Thumb-2 technology builds on the success of Thumb, the innovative
+	  high code density instruction set for ARM microprocessor cores, to
+	  increase the power of the ARM microprocessor core available to
+	  developers of low cost, high performance systems.
+
+	  The technology is backwards compatible with existing ARM and Thumb
+	  solutions, while significantly extending the features available to
+	  the Thumb instructions set. This allows more of the application to
+	  benefit from the best in class code density of Thumb.
+
+	  For performance optimized code Thumb-2 technology uses 31 percent
+	  less memory to reduce system cost, while providing up to 38 percent
+	  higher performance than existing high density code, which can be used
+	  to prolong battery-life or to enrich the product feature set. Thumb-2
+	  technology is featured in the  processor, and in all ARMv7
+	  architecture-based processors.
+
+config ISA_ARM
+	bool
+	help
+	  From: https://developer.arm.com/products/architecture/instruction-sets/a32-and-t32-instruction-sets
+
+	  A32 instructions, known as Arm instructions in pre-Armv8 architectures,
+	  are 32 bits wide, and are aligned on 4-byte boundaries. A32 instructions
+	  are supported by both A-profile and R-profile architectures.
+
+	  A32 was traditionally used in applications requiring the highest
+	  performance, or for handling hardware exceptions such as interrupts and
+	  processor start-up. Much of its functionality was subsumed into T32 with
+	  the introduction of Thumb-2 technology.
+
+config DATA_ENDIANNESS_LITTLE
+	bool
+	default y if CPU_CORTEX
+	help
+	  This is driven by the processor implementation, since it is fixed in
+	  hardware. The board should set this value to 'n' if the data is
+	  implemented as big endian.
+
 config CPU_HAS_SYSTICK
 	bool
 	# Omit prompt to signify "hidden" option
@@ -94,6 +154,38 @@ config ARM_NONSECURE_FIRMWARE
 	  resources of the Cortex-M MCU, and, therefore, it shall avoid
 	  accessing them.
 
+config STACK_ALIGN_DOUBLE_WORD
+	bool "Align stacks on double-words (8 octets)"
+	default y
+	help
+	  This is needed to conform to AAPCS, the procedure call standard for
+	  the ARM. It wastes stack space.
+
+config RUNTIME_NMI
+	bool
+	prompt "Attach an NMI handler at runtime"
+	select REBOOT
+	help
+	  The kernel provides a simple NMI handler that simply hangs in a tight
+	  loop if triggered. This fills the requirement that there must be an
+	  NMI handler installed when the CPU boots. If a custom handler is
+	  needed, enable this option and attach it via _NmiHandlerSet().
+
+config FAULT_DUMP
+	int "Fault dump level"
+	default 2
+	range 0 2
+	help
+	  Different levels for display information when a fault occurs.
+
+	  2: The default. Display specific and verbose information. Consumes
+		the most memory (long strings).
+
+	  1: Display general and short information. Consumes less memory
+		(short strings).
+
+	  0: Off.
+
 menu "Architecture Floating Point Options"
 depends on CPU_HAS_FPU
 
@@ -122,6 +214,7 @@ endchoice
 endmenu
 
 source "arch/arm/core/cortex_m/Kconfig"
+source "arch/arm/core/cortex_r/Kconfig"
 
 if CPU_HAS_MPU
 source "arch/arm/core/cortex_m/mpu/Kconfig"

arch/arm/core/cortex_m/Kconfig

@@ -73,34 +73,6 @@ config CPU_CORTEX_M7
 
 if CPU_CORTEX_M
 
-config ISA_THUMB2
-	bool
-	# Omit prompt to signify "hidden" option
-	help
-	  From: http://www.arm.com/products/processors/technologies/instruction-set-architectures.php
-
-	  Thumb-2 technology is the instruction set underlying the ARM Cortex
-	  architecture which provides enhanced levels of performance, energy
-	  efficiency, and code density for a wide range of embedded
-	  applications.
-
-	  Thumb-2 technology builds on the success of Thumb, the innovative
-	  high code density instruction set for ARM microprocessor cores, to
-	  increase the power of the ARM microprocessor core available to
-	  developers of low cost, high performance systems.
-
-	  The technology is backwards compatible with existing ARM and Thumb
-	  solutions, while significantly extending the features available to
-	  the Thumb instructions set. This allows more of the application to
-	  benefit from the best in class code density of Thumb.
-
-	  For performance optimized code Thumb-2 technology uses 31 percent
-	  less memory to reduce system cost, while providing up to 38 percent
-	  higher performance than existing high density code, which can be used
-	  to prolong battery-life or to enrich the product feature set. Thumb-2
-	  technology is featured in the  processor, and in all ARMv7
-	  architecture-based processors.
-
 config CPU_CORTEX_M_HAS_BASEPRI
 	bool
 	# Omit prompt to signify "hidden" option
@@ -267,50 +239,9 @@ config LDREX_STREX_AVAILABLE
 	bool
 	default y
 
-config DATA_ENDIANNESS_LITTLE
-	bool
-	default y
-	help
-	  This is driven by the processor implementation, since it is fixed in
-	  hardware. The board should set this value to 'n' if the data is
-	  implemented as big endian.
-
-config STACK_ALIGN_DOUBLE_WORD
-	bool
-	prompt "Align stacks on double-words (8 octets)"
-	default y
-	help
-	  This is needed to conform to AAPCS, the procedure call standard for
-	  the ARM. It wastes stack space.
-
-config RUNTIME_NMI
-	bool
-	prompt "Attach an NMI handler at runtime"
-	select REBOOT
-	help
-	  The kernel provides a simple NMI handler that simply hangs in a tight
-	  loop if triggered. This fills the requirement that there must be an
-	  NMI handler installed when the CPU boots. If a custom handler is
-	  needed, enable this option and attach it via _NmiHandlerSet().
-
-config FAULT_DUMP
-	int
-	prompt "Fault dump level"
-	default 2
-	range 0 2
-	help
-	  Different levels for display information when a fault occurs.
-
-	  2: The default. Display specific and verbose information. Consumes
-		the most memory (long strings).
-
-	  1: Display general and short information. Consumes less memory
-		(short strings).
-
-	  0: Off.
-
 config XIP
 	default y
+
 endmenu
 
 menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"

arch/arm/core/cortex_r/CMakeLists.txt

@@ -0,0 +1,8 @@
+zephyr_library()
+
+zephyr_library_sources(
+  vector_table.S
+  reset.S
+  fault.c
+  exceptions.c
+  )

arch/arm/core/cortex_r/Kconfig

@@ -0,0 +1,98 @@
+# Kconfig - ARM Cortex-R platform configuration options
+
+#
+# Copyright (c) 2018 Marvell
+# Copyright (c) 2018 Lexmark International, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# NOTE: We have the specific core implementations first and outside of the
+# if CPU_CORTEX_R block so that SoCs can select which core they are using
+# without having to select all the options related to that core.  Everything
+# else is captured inside the if CPU_CORTEX_R block so they are not exposed
+# if one selects a different ARM Cortex Family (Cortex-A or Cortex-M)
+
+
+config CPU_CORTEX_R4
+	bool
+	select CPU_CORTEX_R
+	select ARMV7_R
+	select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU
+	help
+	  This option signifies the use of a Cortex-R4 CPU
+
+if CPU_CORTEX_R
+
+config ARMV7_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	select ISA_ARM
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation, or the use of an ARMv8-R processor
+	  implementation supporting the Main Extension.
+
+	  Notes:
+	  - A Processing Element (PE) with the Main Extension is also
+	  referred to as a Mainline Implementation.
+	  - ARMv7-R compatibility requires the Main Extension.
+
+	  From https://developer.arm.com/products/architecture/m-profile:
+	  The Main Extension provides backwards compatibility
+	  with ARMv7-R.
+
+config ARMV7_R_FP
+	bool
+	depends on ARMV7_R
+	help
+	  This option signifies the use of an ARMv7-R processor
+	  implementation, or the use of an ARMv8-R processor
+	  implementation supporting the Floating-Point Extension.
+
+config ARMV7_EXCEPTION_STACK_SIZE
+	int "Undefined Instruction and Abort stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the undefined
+	  instruction and data abort exception handlers.
+
+config ARMV7_FIQ_STACK_SIZE
+	int "FIQ stack size (in bytes)"
+	default 256
+	help
+	  This option specifies the size of the stack used by the FIQ handler.
+
+config ARMV7_SVC_STACK_SIZE
+	int "SVC stack size (in bytes)"
+	default 512
+	help
+	  This option specifies the size of the stack used by the SVC handler.
+
+config ARMV7_SYS_STACK_SIZE
+	int "SYS stack size (in bytes)"
+	default 1024
+	help
+	  This option specifies the size of the stack used by the system mode.
+
+menu "ARM Cortex-R options"
+	depends on CPU_CORTEX_R
+
+config RUNTIME_NMI
+	def_bool y
+
+config LDREX_STREX_AVAILABLE
+	def_bool y
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config XIP
+	default y
+
+endmenu
+
+endif # CPU_CORTEX_R

arch/arm/core/cortex_r/exceptions.c

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+
+K_THREAD_STACK_DEFINE(_fiq_stack,   CONFIG_ARMV7_FIQ_STACK_SIZE);
+K_THREAD_STACK_DEFINE(_abort_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+K_THREAD_STACK_DEFINE(_undef_stack, CONFIG_ARMV7_EXCEPTION_STACK_SIZE);
+K_THREAD_STACK_DEFINE(_svc_stack,   CONFIG_ARMV7_SVC_STACK_SIZE);
+K_THREAD_STACK_DEFINE(_sys_stack,   CONFIG_ARMV7_SYS_STACK_SIZE);

arch/arm/core/cortex_r/fault.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2018 Lexmark International, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+
+/**
+ *
+ * @brief Fault handler
+ *
+ * This routine is called when fatal error conditions are detected by hardware
+ * and is responsible only for reporting the error. Once reported, it then
+ * invokes the user provided routine _SysFatalErrorHandler() which is
+ * responsible for implementing the error handling policy.
+ *
+ * This is a stub for more exception handling code to be added later.
+ */
+void _Fault(const NANO_ESF *esf)
+{
+	_SysFatalErrorHandler(_NANO_ERR_HW_EXCEPTION, esf);
+}
+
+void _FaultInit(void)
+{
+}