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lines changed Original file line number Diff line number Diff line change 1+ /*
2+ * Copyright (c) 2021, ATL Electronics
3+ *
4+ * SPDX-License-Identifier: Apache-2.0
5+ */
6+
7+ #include <arm/armv7-m.dtsi>
8+
9+ / {
10+ cpus {
11+ #address-cells = <1>;
12+ #size-cells = <0>;
13+
14+ cpu0: cpu@0 {
15+ device_type = "cpu";
16+ compatible = "arm,cortex-m4f";
17+ reg = <0>;
18+ #address-cells = <1>;
19+ #size-cells = <1>;
20+
21+ mpu: mpu@e000ed90 {
22+ compatible = "arm,armv7m-mpu";
23+ reg = <0xe000ed90 0x40>;
24+ arm,num-mpu-regions = <8>;
25+ };
26+ };
27+ };
28+
29+ soc {
30+ sram0: memory@20000000 {
31+ compatible = "mmio-sram";
32+ };
33+
34+ fmc: flash-controller@40022000 {
35+ compatible = "gd,gd32-flash-controller";
36+ label = "FLASH_CTRL";
37+ reg = <0x40022000 0x400>;
38+ peripheral-id = <6>;
39+
40+ #address-cells = <1>;
41+ #size-cells = <1>;
42+
43+ flash0: flash@8000000 {
44+ compatible = "soc-nv-flash";
45+ label = "FLASH_0";
46+ };
47+ };
48+ };
49+ };
50+
51+ &nvic {
52+ arm,num-irq-priority-bits = <4>;
53+ };
Original file line number Diff line number Diff line change 1+ /*
2+ * Copyright (c) 2021 ATL Electronics
3+ *
4+ * SPDX-License-Identifier: Apache-2.0
5+ */
6+
7+ #include <mem.h>
8+ #include <gigadevice/gd32f403.dtsi>
9+
10+ / {
11+ soc {
12+ flash-controller@40022000 {
13+ flash0: flash@8000000 {
14+ reg = <0x08000000 DT_SIZE_K(512)>;
15+ };
16+ };
17+
18+ sram0: memory@20000000 {
19+ reg = <0x20000000 DT_SIZE_K(96)>;
20+ };
21+ };
22+ };
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