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dts: mcxa166,mcxa276: add dts for MCXA166 and MCXA276
add dts for device MCXA166 and MCXA276 Signed-off-by: Peter Wang <[email protected]>
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‎dts/arm/nxp/nxp_mcxa166.dtsi

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/*
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* Copyright 2024-2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,port-pinctrl";
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status = "okay";
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};
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soc {
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syscon: syscon@40091000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x40091000 0x4000>;
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#clock-cells = <1>;
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reset: reset {
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compatible = "nxp,lpc-syscon-reset";
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#reset-cells = <1>;
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};
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};
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sramx: memory@4000000 {
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(8)>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(240)>;
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};
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porta: pinmux@400bc000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bc000 0x1000>;
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clocks = <&syscon MCUX_PORT0_CLK>;
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};
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portb: pinmux@400bd000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bd000 0x1000>;
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clocks = <&syscon MCUX_PORT1_CLK>;
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};
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portc: pinmux@400be000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400be000 0x1000>;
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clocks = <&syscon MCUX_PORT2_CLK>;
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};
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portd: pinmux@400bf000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bf000 0x1000>;
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clocks = <&syscon MCUX_PORT3_CLK>;
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};
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porte: pinmux@400c0000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400c0000 0x1000>;
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clocks = <&syscon MCUX_PORT4_CLK>;
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};
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gpio0: gpio@40102000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40102000 0x1000>;
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interrupts = <71 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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};
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gpio1: gpio@40103000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40103000 0x1000>;
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interrupts = <72 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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};
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gpio2: gpio@40104000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40104000 0x1000>;
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interrupts = <73 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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};
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gpio3: gpio@40105000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40105000 0x1000>;
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interrupts = <74 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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};
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gpio4: gpio@40106000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40106000 0x1000>;
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interrupts = <75 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porte>;
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};
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lpuart2: lpuart@400a1000 {
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compatible = "nxp,lpuart";
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status = "disabled";
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reg = <0x400a1000 0x1000>;
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interrupts = <33 0>;
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clocks = <&syscon MCUX_LPUART2_CLK>;
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};
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fmu: flash-controller@40095000 {
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compatible = "nxp,msf1";
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reg = <0x40095000 0x1000>;
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interrupts = <12 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_M(1)>;
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erase-block-size = <8192>;
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write-block-size = <128>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

‎dts/arm/nxp/nxp_mcxa276.dtsi

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/*
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* Copyright 2024-2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,port-pinctrl";
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status = "okay";
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};
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soc {
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syscon: syscon@40091000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x40091000 0x4000>;
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#clock-cells = <1>;
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reset: reset {
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compatible = "nxp,lpc-syscon-reset";
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#reset-cells = <1>;
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};
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};
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sramx: memory@4000000 {
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(8)>;
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(240)>;
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};
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porta: pinmux@400bc000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bc000 0x1000>;
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clocks = <&syscon MCUX_PORT0_CLK>;
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};
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portb: pinmux@400bd000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bd000 0x1000>;
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clocks = <&syscon MCUX_PORT1_CLK>;
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};
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portc: pinmux@400be000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400be000 0x1000>;
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clocks = <&syscon MCUX_PORT2_CLK>;
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};
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portd: pinmux@400bf000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400bf000 0x1000>;
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clocks = <&syscon MCUX_PORT3_CLK>;
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};
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porte: pinmux@400c0000 {
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compatible = "nxp,port-pinmux";
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reg = <0x400c0000 0x1000>;
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clocks = <&syscon MCUX_PORT4_CLK>;
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};
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gpio0: gpio@40102000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40102000 0x1000>;
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interrupts = <71 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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};
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gpio1: gpio@40103000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40103000 0x1000>;
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interrupts = <72 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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};
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gpio2: gpio@40104000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40104000 0x1000>;
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interrupts = <73 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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};
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gpio3: gpio@40105000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40105000 0x1000>;
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interrupts = <74 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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};
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gpio4: gpio@40106000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x40106000 0x1000>;
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interrupts = <75 0>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porte>;
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};
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lpuart2: lpuart@400a1000 {
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compatible = "nxp,lpuart";
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status = "disabled";
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reg = <0x400a1000 0x1000>;
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interrupts = <33 0>;
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clocks = <&syscon MCUX_LPUART2_CLK>;
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};
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fmu: flash-controller@40095000 {
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compatible = "nxp,msf1";
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reg = <0x40095000 0x1000>;
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interrupts = <12 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_M(1)>;
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erase-block-size = <8192>;
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write-block-size = <128>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};

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