boards: arm: mimxrt595_evk: enable APS64 PSRAM on FlexSPI2

Enable APS64 PSRAM on FlexSPI2 bus, running at 200MHz. This PSRAM is
accessible via the memory mapped AHB region for FlexSPI2 when
CONFIG_MEMC=y

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi

@@ -73,4 +73,29 @@
 		};
 	};
 
+	pinmux_flexspi2: pinmux_flexspi2 {
+		group0 {
+			pinmux =
+				<FLEXSPI1_SCLK_PIO4_11>,
+				<FLEXSPI1_DATA0_PIO4_12>,
+				<FLEXSPI1_DATA1_PIO4_13>,
+				<FLEXSPI1_DATA2_PIO4_14>,
+				<FLEXSPI1_DATA3_PIO4_15>,
+				<FLEXSPI1_DATA4_PIO5_15>,
+				<FLEXSPI1_DATA5_PIO5_16>,
+				<FLEXSPI1_DATA6_PIO5_17>,
+				<FLEXSPI1_DATA7_PIO5_18>,
+				<FLEXSPI1_SS0_N_PIO4_18>;
+			slew-rate = "normal";
+			input-enable;
+			drive-strength = "high";
+		};
+		group1 {
+			pinmux = <FLEXSPI1_DQS_PIO4_16>;
+			slew-rate = "normal";
+			input-enable;
+			drive-strength = "high";
+			bias-pull-down;
+		};
+	};
 };

boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts

@@ -317,3 +317,30 @@ zephyr_udc0: &usbhs {
 		};
 	};
 };
+
+&flexspi2 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_flexspi2>;
+	pinctrl-names = "default";
+	rx-clock-source = <3>;
+	ahb-prefetch;
+	ahb-bufferable;
+	ahb-cacheable;
+	ahb-read-addr-opt;
+	aps6408l: aps6408l@0 {
+		compatible = "nxp,imx-flexspi-aps6408l";
+		/* APS6408L is 8MB, 64MBit pSRAM */
+		size = <DT_SIZE_M(8 * 8)>;
+		reg = <0>;
+		spi-max-frequency = <198000000>;
+		status = "okay";
+		cs-interval-unit = <1>;
+		cs-interval = <5>;
+		cs-hold-time = <3>;
+		cs-setup-time = <3>;
+		data-valid-time = <1>;
+		column-space = <0>;
+		ahb-write-wait-unit = <2>;
+		ahb-write-wait-interval = <0>;
+	};
+};