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samples: sdhc: add SDIO CMD52 read/write sample.
The sample performs the following: - Initializes the SDIO interface. - Reads a register using CMD52. - Writes a value using CMD52. - Verifies the write by reading back the reg. Signed-off-by: Sara Touqan <[email protected]>
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samples/drivers/sdhc/index.rst

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.. zephyr:code-sample-category:: sdhc
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:name: Secure Digital Host Controller (SDHC)
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:show-listing:
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These samples demonstrate how to use the :ref:`sdhc` driver API.
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(sdhc_read_write)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})
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.. _sdhc:
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.. zephyr:code-sample:: sdhc
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:name: SDHC direct read/write
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:relevant-api: sdhc_interface
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Overview
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********
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This sample demonstrates how to use the SDIO CMD52 (direct) command to read
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from and write to SDIO registers using the Zephyr SDHC API.
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The sample performs the following:
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- Initializes the SDIO interface
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- Reads a register using CMD52
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- Writes a value using CMD52
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- Verifies the write by reading back and checking the result
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Requirements
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************
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- A board with SDIO host (SDMMC) support.
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- A connected SDIO device (e.g., Wi-Fi module)
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- Proper DTS configuration enabling SDMMC
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Building and Running
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********************
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.. zephyr-app-commands::
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:zephyr-app: samples/drivers/sdhc
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:board: arduino_giga_r1/stm32h747xx/m7
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:goals: build flash
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:compact:
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Sample output
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*************
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Connect to the console output to observe CMD52 results.
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When the sample runs successfully, you should see output similar to the following:
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.. code-block:: console
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I: SDIO Init Passed Successfully
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I: Card does not support CMD8, assuming legacy card
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WLAN MAC Address : FC:84:A7:38:E4:49
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WLAN Firmware : wl0: Jul 18 2021 19:15:39 version 7.45.98.120 (56df937 CY) FWID 01-69db62cf
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WLAN CLM : API: 12.2 Data: 9.10.39 Compiler: 1.29.4 ClmImport: 1.36.3 Creation: 2021-07-18 19:03:20
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WHD VERSION : 3.3.2.25168 : v3.3.2 : GCC 12.2 : 2024-12-06 06:53:17 +0000
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*** Booting Zephyr OS build v4.1.0-6920-ga34249351280 ***
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I: CMD52 READ passed: data = 0x05
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I: CMD52 WRITE passed: wrote 0x07
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I: read data after write was as expected, data = 0x07
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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SDMMC_STM32=y
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CONFIG_CYW4343W=y
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CONFIG_CYW4343W_MURATA_1DX=y
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CONFIG_LOG_MODE_DEFERRED=y
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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SDMMC_STM32=y
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CONFIG_CYW4343W=y
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CONFIG_CYW4343W_MURATA_1DX=y
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CONFIG_LOG_MODE_DEFERRED=y
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# Copyright (c) 2025 EXALT Technologies.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SDMMC_STM32=y
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CONFIG_CYW4343W=y
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CONFIG_CYW4343W_MURATA_1DX=y
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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&boot_partition{
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reg = <0x00000000 0x00020000>;
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};
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&scratch_partition {
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reg = <0x00020000 0x00020000>;
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};
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&slot0_partition {
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reg = <0x00040000 0x001C0000>;
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};
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&slot1_partition {
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reg = <0x00200000 0x001C0000>;
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};
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CONFIG_LOG=y
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CONFIG_LOG_DEFAULT_LEVEL=3
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CONFIG_LOG_MODE_MINIMAL=y
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CONFIG_SDHC=y
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CONFIG_NETWORKING=y
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CONFIG_SDIO_STACK=y
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CONFIG_WIFI=y
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CONFIG_SDHC_INIT_PRIORITY=75
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CONFIG_MAIN_STACK_SIZE=20480
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CONFIG_HEAP_MEM_POOL_SIZE=24576
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CONFIG_CACHE_MANAGEMENT=y
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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <stdio.h>
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#include <assert.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/sd/sdio.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/sdhc.h>
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LOG_MODULE_REGISTER(sdio_sample, LOG_LEVEL_INF);
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static int cmd52_read(const struct device *dev, struct sdhc_command *cmd, enum sdio_func_num func,
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uint32_t reg_addr)
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{
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cmd->opcode = SDIO_RW_DIRECT;
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cmd->arg = (func << SDIO_CMD_ARG_FUNC_NUM_SHIFT) |
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((reg_addr & SDIO_CMD_ARG_REG_ADDR_MASK) << SDIO_CMD_ARG_REG_ADDR_SHIFT);
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cmd->response_type = (SD_RSP_TYPE_R5);
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cmd->timeout_ms = CONFIG_SD_CMD_TIMEOUT;
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return sdhc_request(dev, cmd, NULL);
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}
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static int cmd52_write(const struct device *dev, struct sdhc_command *cmd, enum sdio_func_num func,
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uint32_t reg_addr, uint8_t data_in)
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{
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cmd->opcode = SDIO_RW_DIRECT;
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cmd->arg = (func << SDIO_CMD_ARG_FUNC_NUM_SHIFT) |
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((reg_addr & SDIO_CMD_ARG_REG_ADDR_MASK) << SDIO_CMD_ARG_REG_ADDR_SHIFT);
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cmd->arg |= data_in;
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cmd->arg |= BIT(SDIO_CMD_ARG_RW_SHIFT);
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if (data_in) {
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cmd->arg |= BIT(SDIO_DIRECT_CMD_ARG_RAW_SHIFT);
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}
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cmd->response_type = (SD_RSP_TYPE_R5);
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cmd->timeout_ms = CONFIG_SD_CMD_TIMEOUT;
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return sdhc_request(dev, cmd, NULL);
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}
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int main(void)
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{
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int res;
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uint8_t data;
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uint8_t read_data = 0;
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struct sdhc_command cmd = {0};
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enum sdio_func_num func_num = SDIO_FUNC_NUM_0;
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const struct device *sdmmc_dev = DEVICE_DT_GET(DT_NODELABEL(sdhc));
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if (!device_is_ready(sdmmc_dev)) {
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LOG_ERR("SDHC %s is not ready", sdmmc_dev->name);
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return -1;
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}
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res = cmd52_read(sdmmc_dev, &cmd, func_num, SDIO_CCCR_INT_EN);
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if (res == 0) {
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data = cmd.response[0U];
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LOG_INF("CMD52 READ passed: data = 0x%02X", cmd.response[0U]);
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} else {
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LOG_ERR("CMD52 READ failed");
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return -1;
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}
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data = data | BIT(SDIO_FUNC_NUM_1);
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/* Enabling function 1 interrupt by writing to SDIO_CCCR_INT_EN */
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res = cmd52_write(sdmmc_dev, &cmd, func_num, SDIO_CCCR_INT_EN, data);
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if (res == 0) {
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LOG_INF("CMD52 WRITE passed: wrote 0x%02X", data);
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} else {
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LOG_ERR("CMD52 WRITE failed for data 0x%02X", data);
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return -1;
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}
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res = cmd52_read(sdmmc_dev, &cmd, func_num, SDIO_CCCR_INT_EN);
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if (res == 0) {
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read_data = cmd.response[0U];
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if (read_data == data) {
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LOG_INF("read data after write was as expected, data = 0x%02X", read_data);
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} else {
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LOG_ERR("read data was not as expected, expected 0x%02X, got 0x%02X",
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data, read_data);
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return -1;
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}
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} else {
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LOG_ERR("CMD52 READ (post-write) failed");
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return -1;
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}
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return 0;
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}

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