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boards: nordic: Add initial support for nRF54LM20A/ns
Add board files for nRF54LM20A/ns. Update existing nRF54LM20A board files to support this. Signed-off-by: Dag Erik Gjørvad <[email protected]>
1 parent 376ca57 commit ac7bc67

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-44
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‎boards/nordic/nrf54lm20dk/Kconfig‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
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if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS
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config NRF_TRUSTZONE_FLASH_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the flash region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral-specific symbols.
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config NRF_TRUSTZONE_RAM_REGION_SIZE
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hex
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default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
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help
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This defines the RAM region size from the TrustZone perspective.
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It is used when configuring the TrustZone and when setting alignments
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requirements for the partitions.
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This abstraction allows us to configure TrustZone without depending
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on peripheral specific symbols.
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endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS

‎boards/nordic/nrf54lm20dk/Kconfig.defconfig‎

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@@ -7,3 +7,12 @@ config HW_STACK_PROTECTION
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default ARCH_HAS_STACK_PROTECTION
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endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
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if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS
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# By default, if we build for a Non-Secure version of the board,
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# enable building with TF-M as the Secure Execution Environment.
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config BUILD_WITH_TFM
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default y
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endif # BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS

‎boards/nordic/nrf54lm20dk/Kconfig.nrf54lm20dk‎

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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF54LM20DK
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select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP
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select SOC_NRF54LM20A_ENGA_CPUAPP if BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP || BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS
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select SOC_NRF54LM20A_ENGA_CPUFLPR if BOARD_NRF54LM20DK_NRF54LM20A_CPUFLPR

‎boards/nordic/nrf54lm20dk/board.cmake‎

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@@ -7,5 +7,13 @@ elseif(CONFIG_SOC_NRF54LM20A_ENGA_CPUFLPR)
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board_runner_args(jlink "--speed=4000")
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endif()
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if(CONFIG_BOARD_NRF54LM20DK_NRF54LM20A_CPUAPP_NS)
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set(TFM_PUBLIC_KEY_FORMAT "full")
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endif()
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if(CONFIG_TFM_FLASH_MERGED_BINARY)
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set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
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endif()
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

‎boards/nordic/nrf54lm20dk/board.yml‎

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socs:
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- name: nrf54lm20a
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variants:
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- name: ns
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cpucluster: cpuapp
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- name: xip
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cpucluster: cpuflpr
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runners:
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuapp/ns
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
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'--erase':
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuapp/ns
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip
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'--reset':
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groups:
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- boards:
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- nrf54lm20dk/nrf54lm20a/cpuapp
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- nrf54lm20dk/nrf54lm20a/cpuapp/ns
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- nrf54lm20dk/nrf54lm20a/cpuflpr
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- nrf54lm20dk/nrf54lm20a/cpuflpr/xip

‎boards/nordic/nrf54lm20dk/nrf54lm20a_cpuapp_common.dtsi‎

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status = "okay";
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};
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(449)>;
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};
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slot0_ns_partition: partition@80400 {
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label = "image-0-nonsecure";
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reg = <0x80400 DT_SIZE_K(449)>;
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};
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slot1_partition: partition@f0800 {
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label = "image-1";
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reg = <0xf0800 DT_SIZE_K(449)>;
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};
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slot1_ns_partition: partition@160c00 {
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label = "image-1-nonsecure";
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reg = <0x160c00 DT_SIZE_K(449)>;
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};
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storage_partition: partition@1d1000 {
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label = "storage";
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reg = <0x1d1000 DT_SIZE_K(36)>;
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};
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};
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};
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&uart20 {
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status = "okay";
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};
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status = "okay";
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};
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&bt_hci_controller {
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status = "okay";
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};
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&ieee802154 {
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status = "okay";
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};

‎boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp.dts‎

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/dts-v1/;
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#include "nrf54lm20a_cpuapp_common.dtsi"
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#include <nordic/nrf54lm20a_partition.dtsi>
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/ {
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compatible = "nordic,nrf54lm20dk_nrf54lm20a-cpuapp";
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status = "okay";
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};
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&uart30 {
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status = "okay";
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};
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/* Get a node label for wi-fi spi to use in shield files */
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wifi_spi: &spi22 {};

‎boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.dts‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#define USE_NON_SECURE_ADDRESS_MAP 1
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#include "nrf54lm20a_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54lm20dk_nrf54lm20a-cpuapp-ns";
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model = "Nordic nRF54LM20 DK nRF54LM20A Application MCU Non-Secure";
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chosen {
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zephyr,code-partition = &slot0_ns_partition;
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zephyr,sram = &sram0_ns;
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zephyr,entropy = &psa_rng;
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};
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psa_rng: psa-rng {
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status = "okay";
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};
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};
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/ {
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/*
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* Default SRAM planning when building for nRF54LM20A with ARM TrustZone-M support
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* - Lowest 208 kB SRAM allocated to Secure image (sram0_s).
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* - Upper 208 kB SRAM allocated to Non-Secure image (sram0_ns).
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*
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* nRF54LM20A has 512 kB of volatile memory (SRAM), but 96kB is allocated for the FLPR MCU.
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* This static layout needs to be the same with the upstream TF-M layout in the
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* header flash_layout.h of the relevant platform. Any updates in the layout
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* needs to happen both in the flash_layout.h and in this file at the same time.
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*/
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sram0_s: image_s@20000000 {
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/* Secure image memory */
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reg = <0x20000000 DT_SIZE_K(208)>;
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};
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sram0_ns: image_ns@20034000 {
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/* Non-Secure image memory */
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reg = <0x20034000 DT_SIZE_K(208)>;
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};
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};
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};
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/* Include default memory partition configuration file */
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#include <nordic/nrf54lm20a_ns_partition.dtsi>

‎boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns.yaml‎

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identifier: nrf54lm20dk/nrf54lm20a/cpuapp/ns
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name: nRF54lm20-DK-nRF54lm20a-Application-Non-Secure
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- zephyr
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ram: 208
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flash: 1356
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supported:
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- adc
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- counter
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- dmic
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- gpio
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- i2c
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- i2s
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- pwm
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- spi
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- usbd
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- watchdog
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vendor: nordic
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sysbuild: true

‎boards/nordic/nrf54lm20dk/nrf54lm20dk_nrf54lm20a_cpuapp_ns_defconfig‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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# Enable MPU
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CONFIG_ARM_MPU=y
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable TrustZone-M
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CONFIG_ARM_TRUSTZONE_M=y
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# This Board implies building Non-Secure firmware
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CONFIG_TRUSTED_EXECUTION_NONSECURE=y
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Don't enable the cache in the non-secure image as it is a
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# secure-only peripheral on 54l
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CONFIG_CACHE_MANAGEMENT=n
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CONFIG_EXTERNAL_CACHE=n
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# Start SYSCOUNTER on driver init
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CONFIG_NRF_GRTC_START_SYSCOUNTER=y
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# Disable TFM BL2 since it is not supported
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CONFIG_TFM_BL2=n
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# Support for silence logging is not supported at the moment
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# Tracked by: NCSDK-31930
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CONFIG_TFM_LOG_LEVEL_SILENCE=n
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# The oscillators are configured as secure and cannot be configured
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# from the non secure application directly. This needs to be set
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# otherwise nrfx will try to configure them, resulting in a bus
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# fault.
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CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y

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