tests/drivers/clock_control: stm32u5: Fix pll_msis_80 test config

PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay renamed to tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_40.overlay

@@ -21,17 +21,17 @@
 
 &pll1 {
 	div-m = <1>;
-	mul-n = <40>;
-	div-q = <1>;
-	div-r = <1>;
+	mul-n = <80>;
+	div-q = <4>;
+	div-r = <4>;
 	clocks = <&clk_msis>;
 	status = "okay";
 };
 
 &rcc {
 	clocks = <&pll1>;
 	ahb-prescaler = <2>;              /* Use AHB prescaler to reduce HCLK */
-	clock-frequency = <DT_FREQ_M(80)>;
+	clock-frequency = <DT_FREQ_M(40)>;
 	apb1-prescaler = <1>;
 	apb2-prescaler = <1>;
 	apb3-prescaler = <1>;

tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml

@@ -4,8 +4,8 @@ common:
 tests:
   drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay"
-  drivers.stm32_clock_configuration.u5.pll_msis_hab_2_80:
-    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_80.overlay"
+  drivers.stm32_clock_configuration.u5.pll_msis_hab_2_40:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_40.overlay"
   drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
     extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay"
   drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40: