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dts: bingdings: timer: add sifli,sf32lb-atim
add sifli,sf32lb-atim bingdings Signed-off-by: Qingsong Gou <[email protected]>
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# Copyright (c) 2025, Qingsong Gou <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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description: Sifli SF32LB ATIM
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compatible: "sifli,sf32lb-atim"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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sifli,prescaler:
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type: int
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default: 0
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required: true
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description: |
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Counter prescaler from 0 to 65535. default reset value is 'not divided'
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The clock frequency to the counter is the input frequency divided by (prescaler + 1).
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For example, if the input clock is 48 MHz and the desired counter clock is 1 MHz,
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set this property to 47.

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