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drivers: mspi: Support MSPI driver for STM32
This commit introduces support for the mspi and ospi drivers on STM32, enabling functionality APIs for MSPI/OSPI/QSPI host controllers.. Signed-off-by: Sara Touqan <[email protected]> Signed-off-by: Sarah Younis <[email protected]> Signed-off-by: Mohammad Odeh <[email protected]>
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‎drivers/mspi/CMakeLists.txt‎

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@@ -8,3 +8,6 @@ zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_AP5 mspi_ambiq_ap5.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ_TIMING_SCAN mspi_ambiq_timing_scan.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_DW mspi_dw.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_EMUL mspi_emul.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_STM32_OSPI mspi_stm32_ospi.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_STM32_QSPI mspi_stm32_qspi.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_STM32_XSPI mspi_stm32_xspi.c)

‎drivers/mspi/Kconfig‎

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@@ -62,5 +62,6 @@ source "subsys/logging/Kconfig.template.log_config"
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source "drivers/mspi/Kconfig.ambiq"
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source "drivers/mspi/Kconfig.dw"
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source "drivers/mspi/Kconfig.mspi_emul"
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source "drivers/mspi/Kconfig.stm32"
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endif # MSPI

‎drivers/mspi/Kconfig.stm32‎

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# STM32 MSPI flash driver configuration options
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# Copyright (c) 2025 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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config MSPI_STM32_XSPI
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bool "STM32 XSPI Controller driver"
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depends on DT_HAS_ST_STM32_XSPI_CONTROLLER_ENABLED
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select USE_STM32_HAL_XSPI
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select USE_STM32_LL_DLYB
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select DMA
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select USE_STM32_HAL_DMA
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select USE_STM32_HAL_DMA_EX
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imply MSPI_XIP
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default y
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help
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Enable driver for STM32 family of processors.
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config MSPI_STM32_QSPI
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bool "STM32 QSPI Controller driver"
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default y
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depends on DT_HAS_ST_STM32_QSPI_CONTROLLER_ENABLED
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select USE_STM32_HAL_QSPI
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select DMA
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select USE_STM32_HAL_DMA
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select USE_STM32_HAL_DMA_EX
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select USE_STM32_HAL_MDMA
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imply MSPI_XIP
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help
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Enable QSPI driver for STM32 family of processors.
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#DT_STM32_OCTOSPI_HAS_DMA := $(dt_compat_any_has_prop,$(DT_COMPAT_ST_STM32_OSPI),dmas)
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config MSPI_STM32_OSPI
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bool "STM32 OSPI Controller driver"
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default y
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depends on DT_HAS_ST_STM32_OSPI_CONTROLLER_ENABLED
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select USE_STM32_HAL_OSPI if !SOC_SERIES_STM32H5X
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select USE_STM32_LL_DLYB if (SOC_SERIES_STM32H5X || SOC_SERIES_STM32U5X)
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select USE_STM32_HAL_MDMA if SOC_SERIES_STM32H7X
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select DMA
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select USE_STM32_HAL_DMA
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select USE_STM32_HAL_DMA_EX
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help
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Enable OSPI driver for STM32 family of processors.
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config MSPI_BUFFER_ALIGNMENT
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int
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default 32
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help
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Some MSPI host controllers require alignment of their data buffers
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in order for DMA to work correctly. This represents the alignment
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of buffers required in bytes.
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config MSPI_STM32_ALLOW_WRITE_IN_MEMMAP
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bool "Allow write in MEMMAP mode"
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default n
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help
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Some MSPI host controllers allow to write in memory map mode.

‎drivers/mspi/mspi_stm32.h‎

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/*
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* Copyright (c) 2025 EXALT Technologies.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_MSPI_STM32_H_
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#define ZEPHYR_DRIVERS_MSPI_STM32_H_
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/* Macro to check if any xspi device has a domain clock or more */
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#define MSPI_STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_CLOCKS_HAS_IDX(DT_INST_PARENT(inst), 1) ||
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#define MSPI_STM32_INST_DEV_DOMAIN_CLOCK_SUPPORT \
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(DT_INST_FOREACH_STATUS_OKAY(MSPI_STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
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/* This symbol takes the value 1 if device instance has a domain clock in its dts */
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#if MSPI_STM32_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define MSPI_STM32_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define MSPI_STM32_DOMAIN_CLOCK_SUPPORT 0
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#endif
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#define MSPI_STM32_FIFO_THRESHOLD 4U
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#define MSPI_MAX_FREQ 250000000
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#define MSPI_MAX_DEVICE 2
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#if defined(CONFIG_SOC_SERIES_STM32U5X)
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/* Valid range is [1, 256] */
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#define MSPI_STM32_CLOCK_PRESCALER_MIN 1U
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#define MSPI_STM32_CLOCK_PRESCALER_MAX 256U
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#define MSPI_STM32_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / (prescaler))
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#else
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/* Valid range is [0, 255] */
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#define MSPI_STM32_CLOCK_PRESCALER_MIN 0U
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#define MSPI_STM32_CLOCK_PRESCALER_MAX 255U
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#define MSPI_STM32_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U))
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#endif
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#define MSPI_STM32_WRITE_REG_MAX_TIME 40U
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#define MSPI_STM32_MAX_FREQ 48000000
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#define MSPI_STM32_CMD_WRSR 0x01 /* Write status register */
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#define MSPI_STM32_CMD_RDSR 0x05 /* Read status register */
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#define MSPI_STM32_CMD_READ 0x03 /* Read data */
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#define MSPI_STM32_CMD_READ_FAST 0x0B /* Read data */
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#define MSPI_STM32_CMD_PP 0x02 /* Page program */
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#define MSPI_STM32_CMD_READ_4B 0x13 /* Read data 4 Byte Address */
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#define MSPI_STM32_CMD_READ_FAST_4B 0x0C /* Fast Read 4 Byte Address */
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#define MSPI_STM32_CMD_PP_4B 0x12 /* Page Program 4 Byte Address */
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#define MSPI_STM32_CMD_WREN 0x06 /* Write enable */
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#define MSPI_STM32_CMD_RDPD 0xAB /* Release from Deep Power Down */
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#define MSPI_STM32_CMD_RD_CFGREG2 0x71 /* Read config register 2 */
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#define MSPI_STM32_CMD_WR_CFGREG2 0x72 /* Write config register 2 */
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#define MSPI_STM32_CMD_SE 0x20 /* Sector erase */
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#define MSPI_STM32_CMD_SE_4B 0x21 /* Sector erase 4 byte address*/
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#define MSPI_STM32_OCMD_RDSR 0x05FA /* Octal Read status register */
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#define MSPI_STM32_OCMD_RD 0xEC13 /* Octal IO read command */
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#define MSPI_STM32_OCMD_PAGE_PRG 0x12ED /* Octal Page Prog */
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#define MSPI_STM32_OCMD_WREN 0x06F9 /* Octal Write enable */
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#define MSPI_STM32_OCMD_DTR_RD 0xEE11 /* Octal IO DTR read command */
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#define MSPI_STM32_OCMD_WR_CFGREG2 0x728D /* Octal Write configuration Register2 */
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#define MSPI_STM32_OCMD_RD_CFGREG2 0x718E /* Octal Read configuration Register2 */
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#define MSPI_STM32_OCMD_SE 0x21DE /* Octal Sector erase */
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/* Flash Auto-polling values */
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#define MSPI_STM32_WREN_MATCH 0x02
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#define MSPI_STM32_WREN_MASK 0x02
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#define MSPI_STM32_WEL_MATCH 0x00
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#define MSPI_STM32_WEL_MASK 0x02
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#define MSPI_STM32_MEM_RDY_MATCH 0x00
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#define MSPI_STM32_MEM_RDY_MASK 0x01
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#define MSPI_STM32_AUTO_POLLING_INTERVAL 0x10
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/* Flash Dummy Cycles values */
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#define MSPI_STM32_DUMMY_REG_OCTAL 4U
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#define MSPI_STM32_DUMMY_REG_OCTAL_DTR 5U
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/* Memory registers address */
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#define MSPI_STM32_REG2_ADDR1 0x0000000
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#define MSPI_STM32_CR2_STR_OPI_EN 0x01
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#define MSPI_STM32_CR2_DTR_OPI_EN 0x02
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#define MSPI_STM32_REG2_ADDR3 0x00000300
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#define MSPI_STM32_CR2_DUMMY_CYCLES_66MHZ 0x07
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typedef void (*irq_config_func_t)(void);
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#ifndef DMA_LOW_PRIORITY_LOW_WEIGHT
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#define DMA_LOW_PRIORITY_LOW_WEIGHT DMA_PRIORITY_LOW
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#endif
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#ifndef DMA_LOW_PRIORITY_MID_WEIGHT
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#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_PRIORITY_MEDIUM
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#endif
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#ifndef DMA_LOW_PRIORITY_HIGH_WEIGHT
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#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_PRIORITY_HIGH
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#endif
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#ifndef DMA_HIGH_PRIORITY
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#define DMA_HIGH_PRIORITY DMA_PRIORITY_VERY_HIGH
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#endif
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enum mspi_access_mode {
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MSPI_ACCESS_ASYNC = 1,
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MSPI_ACCESS_SYNC = 2,
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MSPI_ACCESS_DMA = 3
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};
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struct mspi_context {
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struct mspi_xfer xfer;
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int packets_left;
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struct k_sem lock;
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};
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struct mspi_stm32_conf {
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bool use_dma;
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size_t pclk_len;
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irq_config_func_t irq_config;
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struct mspi_cfg mspicfg;
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const struct stm32_pclken *pclken;
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const struct pinctrl_dev_config *pcfg;
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};
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/* Lookup table to set dma priority from the DTS */
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static const uint32_t table_priority[] = {
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DMA_LOW_PRIORITY_LOW_WEIGHT,
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DMA_LOW_PRIORITY_MID_WEIGHT,
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DMA_LOW_PRIORITY_HIGH_WEIGHT,
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DMA_HIGH_PRIORITY,
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};
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/* Lookup table to set dma channel direction from the DTS */
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static const uint32_t table_direction[] = {
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DMA_MEMORY_TO_MEMORY,
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DMA_MEMORY_TO_PERIPH,
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DMA_PERIPH_TO_MEMORY,
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};
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#if CONFIG_DMA_STM32U5
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static const uint32_t table_src_size[] = {
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LL_DMA_SRC_DATAWIDTH_BYTE,
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LL_DMA_SRC_DATAWIDTH_HALFWORD,
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LL_DMA_SRC_DATAWIDTH_WORD,
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};
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static const uint32_t table_dest_size[] = {
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LL_DMA_DEST_DATAWIDTH_BYTE,
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LL_DMA_DEST_DATAWIDTH_HALFWORD,
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LL_DMA_DEST_DATAWIDTH_WORD,
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};
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#else
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static const uint32_t table_m_size[] = {
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LL_DMA_MDATAALIGN_BYTE,
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LL_DMA_MDATAALIGN_HALFWORD,
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LL_DMA_MDATAALIGN_WORD,
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};
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static const uint32_t table_p_size[] = {
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LL_DMA_PDATAALIGN_BYTE,
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LL_DMA_PDATAALIGN_HALFWORD,
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LL_DMA_PDATAALIGN_WORD,
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};
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#endif /* CONFIG_DMA_STM32U5 */
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struct stream {
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DMA_TypeDef *reg;
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const struct device *dev;
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uint32_t channel;
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struct dma_config cfg;
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uint8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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};
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union hmspi_handle {
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#ifdef CONFIG_MSPI_STM32_XSPI
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XSPI_HandleTypeDef xspi;
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#endif
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#ifdef CONFIG_MSPI_STM32_OSPI
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OSPI_HandleTypeDef ospi;
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#endif
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#ifdef CONFIG_MSPI_STM32_QSPI
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QSPI_HandleTypeDef qspi;
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#endif
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};
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/* mspi data includes the controller specific config variable */
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struct mspi_stm32_data {
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union hmspi_handle hmspi;
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uint32_t memmap_base_addr;
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struct mspi_context ctx;
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struct mspi_dev_id *dev_id;
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struct k_mutex lock;
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struct k_sem sync;
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struct mspi_dev_cfg dev_cfg;
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struct mspi_xip_cfg xip_cfg;
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struct stream dma_tx;
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struct stream dma_rx;
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struct stream dma;
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};
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#endif /* ZEPHYR_DRIVERS_MSPI_STM32_H_ */

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