drivers: gpio: rcar: Add R-Car Gen4 support

Renesas Gen4 SoCs GPIO IPs are using one more
register comparing to Gen3 SoCs.

The new "INEN" register is used to enable general input.

Signed-off-by: Aymeric Aillet <[email protected]>

Author: aaillet

drivers/gpio/gpio_rcar.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 IoT.bzh
+ * Copyright (c) 2020-2023 IoT.bzh
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -47,6 +47,7 @@ struct gpio_rcar_data {
 #define FILONOFF 0x28   /* Chattering Prevention On/Off Register */
 #define OUTDTSEL 0x40   /* Output Data Select Register */
 #define BOTHEDGE 0x4c   /* One Edge/Both Edge Select Register */
+#define INEN     0x50	/* General Input Enable Register */
 
 static inline uint32_t gpio_rcar_read(const struct gpio_rcar_cfg *config,
 				      uint32_t offs)
@@ -104,6 +105,11 @@ static void gpio_rcar_config_general_input_output_mode(
 	/* Configure positive logic in POSNEG */
 	gpio_rcar_modify_bit(config, POSNEG, gpio, false);
 
+	/* Select "Input Enable/Disable" in INEN for Gen4 SoCs */
+#ifdef CONFIG_SOC_SERIES_RCAR_GEN4
+	gpio_rcar_modify_bit(config, INEN, gpio, !output);
+#endif
+
 	/* Select "General Input/Output Mode" in IOINTSEL */
 	gpio_rcar_modify_bit(config, IOINTSEL, gpio, false);
 
@@ -231,6 +237,11 @@ static int gpio_rcar_pin_interrupt_configure(const struct device *dev,
 		gpio_rcar_modify_bit(config, BOTHEDGE, pin, true);
 	}
 
+	/* Select "Input Enable" in INEN for Gen4 SoCs */
+#ifdef CONFIG_SOC_SERIES_RCAR_GEN4
+	gpio_rcar_modify_bit(config, INEN, pin, true);
+#endif
+
 	gpio_rcar_modify_bit(config, IOINTSEL, pin, true);
 
 	if (mode == GPIO_INT_MODE_EDGE) {