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Bradley Bolenstephanosio
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tests: fpu_sharing: Support FPU disable test for Cortex-A/R
For testing, assume that the Cortex-A/R platforms are using a GIC interrupt controller. Use the last GIC SGI to trigger an interrupt for the test. Signed-off-by: Bradley Bolen <[email protected]>
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tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c

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@@ -151,7 +151,11 @@ void test_k_float_disable_syscall(void)
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#if defined(CONFIG_ARM) && defined(CONFIG_DYNAMIC_INTERRUPTS)
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#include <arch/cpu.h>
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#else
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#include <interrupt_util.h>
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#endif
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struct k_thread sup_fp_thread;
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K_THREAD_STACK_DEFINE(sup_fp_thread_stack, STACKSIZE);
@@ -180,6 +184,7 @@ static void sup_fp_thread_entry(void)
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/* Determine an NVIC IRQ line that is not currently in use. */
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int i;
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#if defined(CONFIG_CPU_CORTEX_M)
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for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) {
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if (NVIC_GetEnableIRQ(i) == 0) {
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/*
@@ -191,6 +196,13 @@ static void sup_fp_thread_entry(void)
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break;
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}
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}
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#else
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/*
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* SGIs are always enabled by default, so choose the last one
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* for testing.
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*/
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i = GIC_PPI_INT_BASE - 1;
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#endif
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zassert_true(i >= 0,
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"No available IRQ line to use in the test\n");
@@ -203,9 +215,14 @@ static void sup_fp_thread_entry(void)
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NULL,
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0);
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#if defined(CONFIG_CPU_CORTEX_M)
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NVIC_ClearPendingIRQ(i);
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NVIC_EnableIRQ(i);
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NVIC_SetPendingIRQ(i);
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#else
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arch_irq_enable(i);
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trigger_irq(i);
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#endif
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/*
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* Instruction barriers to make sure the NVIC IRQ is

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