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ethernet: stm32: move v2 eth init back
move v2 eth init back into eth_initialize() Signed-off-by: Fin Maaß <[email protected]>
1 parent 6df0e3f commit b0d7838

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-83
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1 file changed

+46
-83
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drivers/ethernet/eth_stm32_hal.c

Lines changed: 46 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -814,6 +814,9 @@ static void generate_mac(uint8_t *mac_addr)
814814

815815
#endif /* NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))) */
816816
#endif
817+
818+
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x", mac_addr[0], mac_addr[1], mac_addr[2],
819+
mac_addr[3], mac_addr[4], mac_addr[5]);
817820
}
818821

819822
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
@@ -847,6 +850,7 @@ static int eth_initialize(const struct device *dev)
847850
struct eth_stm32_hal_dev_data *dev_data = dev->data;
848851
const struct eth_stm32_hal_dev_cfg *cfg = dev->config;
849852
ETH_HandleTypeDef *heth = &dev_data->heth;
853+
HAL_StatusTypeDef hal_ret = HAL_OK;
850854
int ret = 0;
851855

852856
if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
@@ -887,30 +891,62 @@ static int eth_initialize(const struct device *dev)
887891

888892
heth->Init.MACAddr = dev_data->mac_addr;
889893

890-
#if defined(CONFIG_ETH_STM32_HAL_API_V1)
891-
HAL_StatusTypeDef hal_ret = HAL_OK;
894+
/* Initialize semaphores */
895+
k_mutex_init(&dev_data->tx_mutex);
896+
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
897+
898+
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
899+
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
900+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
901+
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
902+
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
903+
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
904+
}
905+
#else
906+
heth->Init.TxDesc = dma_tx_desc_tab;
907+
heth->Init.RxDesc = dma_rx_desc_tab;
908+
#endif
909+
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
910+
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
892911

893912
hal_ret = HAL_ETH_Init(heth);
894913
if (hal_ret != HAL_OK) {
895914
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
896915
return -EIO;
897916
}
898917

899-
/* Initialize semaphores */
900-
k_mutex_init(&dev_data->tx_mutex);
901-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
918+
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
919+
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
920+
/* Enable timestamping of RX packets. We enable all packets to be
921+
* timestamped to cover both IEEE 1588 and gPTP.
922+
*/
923+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
924+
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
925+
#else
926+
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
927+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
928+
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
929+
/* Tx config init: */
930+
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
931+
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
932+
ETH_TX_PACKETS_FEATURES_CRCPAD;
933+
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
934+
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
935+
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
902936

937+
/* prepare tx buffer header */
938+
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
939+
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
940+
}
941+
#else /* CONFIG_ETH_STM32_HAL_API_V2 */
903942
HAL_ETH_DMATxDescListInit(heth, dma_tx_desc_tab,
904943
&dma_tx_buffer[0][0], ETH_TXBUFNB);
905944
HAL_ETH_DMARxDescListInit(heth, dma_rx_desc_tab,
906945
&dma_rx_buffer[0][0], ETH_RXBUFNB);
907946

908-
#endif /* !CONFIG_ETH_STM32_HAL_API_V1 */
947+
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
909948

910-
LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x",
911-
dev_data->mac_addr[0], dev_data->mac_addr[1],
912-
dev_data->mac_addr[2], dev_data->mac_addr[3],
913-
dev_data->mac_addr[4], dev_data->mac_addr[5]);
949+
setup_mac_filter(heth);
914950

915951
return 0;
916952
}
@@ -963,68 +999,6 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
963999

9641000
#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
9651001

966-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
967-
static int eth_init_api_v2(const struct device *dev)
968-
{
969-
HAL_StatusTypeDef hal_ret = HAL_OK;
970-
struct eth_stm32_hal_dev_data *dev_data = dev->data;
971-
ETH_HandleTypeDef *heth = &dev_data->heth;
972-
973-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
974-
for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
975-
heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
976-
heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
977-
}
978-
#else
979-
heth->Init.TxDesc = dma_tx_desc_tab;
980-
heth->Init.RxDesc = dma_rx_desc_tab;
981-
#endif
982-
heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
983-
984-
hal_ret = HAL_ETH_Init(heth);
985-
if (hal_ret == HAL_TIMEOUT) {
986-
/* HAL Init time out. This could be linked to */
987-
/* a recoverable error. Log the issue and continue */
988-
/* driver initialisation */
989-
LOG_ERR("HAL_ETH_Init Timed out");
990-
} else if (hal_ret != HAL_OK) {
991-
LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
992-
return -EINVAL;
993-
}
994-
995-
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
996-
/* Enable timestamping of RX packets. We enable all packets to be
997-
* timestamped to cover both IEEE 1588 and gPTP.
998-
*/
999-
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
1000-
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
1001-
#else
1002-
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
1003-
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
1004-
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
1005-
1006-
/* Initialize semaphores */
1007-
k_mutex_init(&dev_data->tx_mutex);
1008-
k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
1009-
k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
1010-
1011-
/* Tx config init: */
1012-
memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
1013-
tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
1014-
ETH_TX_PACKETS_FEATURES_CRCPAD;
1015-
tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
1016-
ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
1017-
tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
1018-
1019-
/* prepare tx buffer header */
1020-
for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
1021-
dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
1022-
}
1023-
1024-
return 0;
1025-
}
1026-
#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
1027-
10281002
static void set_mac_config(const struct device *dev, struct phy_link_state *state)
10291003
{
10301004
struct eth_stm32_hal_dev_data *dev_data = dev->data;
@@ -1126,7 +1100,6 @@ static void eth_iface_init(struct net_if *iface)
11261100
{
11271101
const struct device *dev = net_if_get_device(iface);
11281102
struct eth_stm32_hal_dev_data *dev_data = dev->data;
1129-
ETH_HandleTypeDef *heth = &dev_data->heth;
11301103
bool is_first_init = false;
11311104

11321105
if (dev_data->iface == NULL) {
@@ -1145,16 +1118,6 @@ static void eth_iface_init(struct net_if *iface)
11451118

11461119
ethernet_init(iface);
11471120

1148-
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
1149-
/* This function requires the Ethernet interface to be
1150-
* properly initialized. In auto-negotiation mode, it reads the speed
1151-
* and duplex settings to configure the driver accordingly.
1152-
*/
1153-
eth_init_api_v2(dev);
1154-
#endif
1155-
1156-
setup_mac_filter(heth);
1157-
11581121
net_if_carrier_off(iface);
11591122

11601123
net_lldp_set_lldpdu(iface);

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