boards: arm: lpcxpresso: update core clock documentation

Update documentation for core clock frequency on LPC55xxx boards, to
indicate that they are clocked from PLL1 at 150MHz by default. Add a
note about the reduction to 96MHz required when using the flash
controller.

Signed-off-by: Daniel DeGrasse <[email protected]>

Author: danieldegrasse

boards/arm/lpcxpresso55s16/doc/index.rst

@@ -138,9 +138,11 @@ the functionality of a pin.
 System Clock
 ============
 
-The LPC55S16 SoC is configured to use the internal FRO at 96MHz as a
-source for the system clock. Other sources for the system clock are
-provided in the SOC, depending on your system requirements.
+The LPC55S16 SoC is configured to use PLL1 clocked from the external 24MHz
+crystal, running at 150MHz as a source for the system clock. When the flash
+controller is enabled, the core clock will be reduced to 96MHz. The application
+may reconfigure clocks after initialization, provided that the core clock is
+always set to 96MHz when flash programming operations are performed.
 
 Serial Port
 ===========

boards/arm/lpcxpresso55s28/doc/index.rst

@@ -125,9 +125,11 @@ the functionality of a pin.
 System Clock
 ============
 
-The LPC55S28 SoC is configured to use the internal FRO at 96MHz as a
-source for the system clock. Other sources for the system clock are
-provided in the SOC, depending on your system requirements.
+The LPC55S28 SoC is configured to use PLL1 clocked from the external 24MHz
+crystal, running at 150MHz as a source for the system clock. When the flash
+controller is enabled, the core clock will be reduced to 96MHz. The application
+may reconfigure clocks after initialization, provided that the core clock is
+always set to 96MHz when flash programming operations are performed.
 
 Serial Port
 ===========

boards/arm/lpcxpresso55s69/doc/index.rst

@@ -256,9 +256,11 @@ Dual Core samples
 System Clock
 ============
 
-The LPC55S69 SoC is configured to use the internal FRO at 96MHz as a source for
-the system clock. Other sources for the system clock are provided in the SOC,
-depending on your system requirements.
+The LPC55S69 SoC is configured to use PLL1 clocked from the external 24MHz
+crystal, running at 150MHz as a source for the system clock. When the flash
+controller is enabled, the core clock will be reduced to 96MHz. The application
+may reconfigure clocks after initialization, provided that the core clock is
+always set to 96MHz when flash programming operations are performed.
 
 Serial Port
 ===========