dts: Enable the xspi flash and psram cases on NXP RT700

Move nxp,xspi.yaml from spi bindings to mtd, it should be flash
controllor rather than simple bus controller.
Delete the xspi flash mx25um51345g bindling yaml file which is useless.
Enable flash and two psrams on RT700 core0 and one psram on core1.

Signed-off-by: Ruijia Wang <[email protected]>

Author: SuperHeroAbner

dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi

@@ -1127,8 +1127,26 @@
 &xspi0 {
 	compatible = "nxp,xspi";
 	status = "disabled";
-	interrupts = <42 0>;
+	interrupts = <118 0>;
 	#address-cells = <1>;
 	#size-cells = <0>;
-	clocks = <&clkctl0 MCUX_XSPI_CLK>;
+	clocks = <&clkctl0 MCUX_XSPI0_CLK>;
+};
+
+&xspi1 {
+	compatible = "nxp,xspi";
+	status = "disabled";
+	interrupts = <119 0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clocks = <&clkctl0 MCUX_XSPI1_CLK>;
+};
+
+&xspi2 {
+	compatible = "nxp,xspi";
+	status = "disabled";
+	interrupts = <120 0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clocks = <&clkctl4 MCUX_XSPI2_CLK>;
 };

dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi

@@ -370,3 +370,12 @@
 		status = "disabled";
 	};
 };
+
+&xspi2 {
+	compatible = "nxp,xspi";
+	status = "disabled";
+	interrupts = <74 0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clocks = <&clkctl4 MCUX_XSPI2_CLK>;
+};

dts/arm/nxp/nxp_rt7xx_common.dtsi

@@ -17,7 +17,7 @@
 	soc {
 		sram: memory@10000000 {
 			ranges = <0x0 0x10000000 0x780000
-			0x20000000 0x30000000 0x780000>;
+				  0x20000000 0x30000000 0x780000>;
 		};
 
 		peripheral: peripheral@50000000 {
@@ -83,8 +83,9 @@
 	};
 
 	sram1: memory@20200000 {
-		compatible = "mmio-sram";
+		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x20200000 DT_SIZE_K(2048)>;
+		zephyr,memory-region = "SRAM1";
 	};
 
 	sram3: memory@205C0000 {

dts/bindings/flash_controller/nxp,xspi-nor.yaml

@@ -0,0 +1,8 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI Flash Controller
+
+compatible: "nxp,xspi-nor"
+
+include: ["nxp,xspi-device.yaml", "jedec,jesd216.yaml"]

dts/bindings/memory-controllers/nxp,xspi-psram.yaml

@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI PSRAM Controller
+
+compatible: "nxp,xspi-psram"
+
+include: ["nxp,xspi-device.yaml"]

dts/bindings/mtd/nxp,xspi-device.yaml

@@ -1,6 +1,30 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP XSPI device
 
-include: [spi-device.yaml, "jedec,jesd216.yaml"]
+include: [base.yaml]
+
+properties:
+  device-name:
+    type: string
+    description: Memory device name.
+
+  size:
+    type: int
+    required: true
+    description: Total memory size in bytes.
+
+  enable-differential-clk:
+    type: boolean
+    description: Enable differential clock pad.
+
+  sample-clk-source:
+    type: int
+    default: 3
+    enum: [1, 2, 3, 5, 9]
+    description: Sample clock source.
+
+  enable-dqs-latency:
+    type: boolean
+    description: Enable DQS latency.

dts/bindings/mtd/nxp,xspi-mx25um51345g.yaml

@@ -0,0 +1,88 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI controller
+
+compatible: "nxp,xspi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  byte-order:
+    type: int
+    default: 3
+    enum: [0, 1, 2, 3]
+    description: |
+      Byte ordering endianness.
+      0 = 64-bit BE, 1 = 32-bit LE, 2 = 32-bit BE, 3 = 64-bit LE
+
+  enable-ahb-write:
+    type: boolean
+    description: Enable AHB write access.
+
+  ahb-buffer-write-flush:
+    type: boolean
+    description: Enable flushing AHB buffer on write or IP access.
+
+  ahb-prefetch:
+    type: boolean
+    description: Enable AHB read prefetch feature.
+
+child-binding:
+  description: NXP XSPI MDAD/FRAD configurations
+
+  properties:
+    # MDAD configuration
+    enable-descriptor-lock:
+      type: int
+      description: Enable descriptor lock
+    mask-type:
+      type: int
+      description: Mask type (0=AND, 1=OR)
+    mask:
+      type: int
+      description: 6-bit mask value
+    master-id-reference:
+      type: int
+      description: Master ID reference value
+    secure-attribute:
+      type: int
+      enum: [1, 2, 3]
+      description: Security attribute setting
+
+    # FRAD configuration
+    start-address:
+      type: int
+      description: Start address of the memory region
+    end-address:
+      type: int
+      description: End address of the memory region
+    tg0-master-access:
+      type: int
+      description: Target group 0 access permissions
+    tg1-master-access:
+      type: int
+      description: Target group 1 access permissions
+    descriptor-lock:
+      type: int
+      enum: [0, 1, 2, 3]
+      description: |
+        Descriptor lock mode:
+        - Disable
+        - Enable till hard reset
+        - Enable except master ID
+        - Enable
+    exclusive-access-lock:
+      type: int
+      enum: [0, 2, 3]
+      description: |
+        Exclusive access lock mode:
+        - Disable
+        - Enable except master ID
+        - Enable