dts: arm: st: h7: correct stm32h723 memory regions

* Corrects SRAM0 size. The `TCM_AXI_SHARED`
  is `000` after reset. That means ITCM
  is shared with SRAM0.
* Adds missing SRAM1,2,4, and ITCM
  regions.
* Adds label and compatible properties
  to the flash section.

Signed-off-by: Georgij Cernysiov <[email protected]>

Author: GeorgeCGV

dts/arm/st/h7/stm32h723.dtsi

@@ -1,16 +1,21 @@
 /*
  * Copyright (c) 2020 Alexander Kozhinov <[email protected]>
+ * Copyright (c) 2022 Georgij Cernysiov <[email protected]>
+ *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <mem.h>
 #include <st/h7/stm32h7.dtsi>
 
 / {
 	soc {
 		flash-controller@52002000 {
 			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
 				write-block-size = <32>;
 				erase-block-size = <DT_SIZE_K(128)>;
+				label = "FLASH_STM32";
 			};
 		};
 
@@ -52,16 +57,44 @@
 		};
 	};
 
-	/* DTCM memory directly coupled to CPU */
+	/* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */
+	sram0: memory@24000000 {
+		reg = <0x24000000 DT_SIZE_K(320)>;
+		compatible = "mmio-sram";
+	};
+
+	/* D2 domain, AHB SRAM */
+	sram1: memory@30000000 {
+		reg = <0x30000000 DT_SIZE_K(16)>;
+		compatible = "zephyr,memory-region", "mmio-sram";
+		zephyr,memory-region = "SRAM1";
+	};
+
+	/* D2 domain, AHB SRAM */
+	sram2: memory@30040000 {
+		reg = <0x30040000 DT_SIZE_K(16)>;
+		compatible = "zephyr,memory-region", "mmio-sram";
+		zephyr,memory-region = "SRAM2";
+	};
+
+	/* D3 domain, AHB SRAM  */
+	sram4: memory@38000000 {
+		reg = <0x38000000 DT_SIZE_K(16)>;
+		compatible = "zephyr,memory-region", "mmio-sram";
+		zephyr,memory-region = "SRAM4";
+	};
+
+	/* Data TCM RAM */
 	dtcm: memory@20000000 {
 		compatible = "zephyr,memory-region", "arm,dtcm";
 		reg = <0x20000000 DT_SIZE_K(128)>;
 		zephyr,memory-region = "DTCM";
 	};
 
-	/* AXI SRAM in D1 domain (AXI bus) */
-	sram0: memory@24000000 {
-		reg = <0x24000000 DT_SIZE_K(128)>;
-		compatible = "mmio-sram";
+	/* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */
+	itcm: memory@0 {
+		compatible = "zephyr,memory-region", "arm,itcm";
+		reg = <0x00000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "ITCM";
 	};
 };