drivers: mipi_dbi: Add defines for color coding

Add defines for color coding of DBI Type A(Motorola 6800)
and B(Intel 8080) bus. This is to comply with the MIPI
Alliance Standard for Display Bus Interface v2.0.

Signed-off-by: Kate Wang <[email protected]>

Author: KATE-WANG-NXP

include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024,2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -110,6 +110,54 @@
 #define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7
 #define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8
 
+/** Color coding for MIPI DBI Type A or Type B interface. */
+/**
+ * For 8-bit data bus width, 1 pixel is sent in 1 cycle. For 16-bit data bus width,
+ * 2 pixels are sent in 1 cycle.
+ */
+#define MIPI_DBI_MODE_RGB332 (0x1 << 4U)
+/**
+ * For 8-bit data bus width, 2 pixels are sent in 3 cycles. For 16-bit data bus width,
+ * 1 pixel is sent in 1 cycle, the high 4 bits are not used.
+ */
+#define MIPI_DBI_MODE_RGB444 (0x2 << 4U)
+/**
+ * For 8-bit data bus width, 1 pixel is sent in 2 cycles. For 16-bit data bus width,
+ * 1 pixel is sent in 1 cycle.
+ */
+#define MIPI_DBI_MODE_RGB565 (0x3 << 4U)
+/**
+ * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 3 cycles, R component first, and the low 2
+ * bits are not used.
+ * For 9-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 2 cycles.
+ * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1,
+ * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in
+ * cycle 1 bits 10-15, cycle 1 bits 2-7 and cycle 2 bits 10-15.
+ * The second pixel's R/G/B components are sent in cycle 2 bits 2-7, cycle 3 bits
+ * 10-15 and cycle 3 bits 2-7.
+ * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's
+ * R/G/B components are sent in cycle 1 bits 2-7, cycle 2 bits 10-15 and cycle 2
+ * bits 2-7.
+ */
+#define MIPI_DBI_MODE_RGB666_1 (0x4 << 4U)
+#define MIPI_DBI_MODE_RGB666_2 (0x5 << 4U)
+/**
+ * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 3 cycles, R component first.
+ * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1,
+ * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in
+ * cycle 1 bits 8-15, cycle 1 bits 0-7 and cycle 2 bits 0-15.
+ * The second pixel's R/G/B components are sent in cycle 2 bits 0-7, cycle 3 bits
+ * 8-15 and cycle 3 bits 0-7.
+ * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's
+ * R/G/B components are sent in cycle 1 bits 0-7, cycle 2 bits 8-15 and cycle 2
+ * bits 0-7.
+ */
+#define MIPI_DBI_MODE_RGB888_1 (0x6 << 4U)
+#define MIPI_DBI_MODE_RGB888_2 (0x7 << 4U)
+
 /** MIPI DBI tearing enable synchronization is disabled. */
 #define MIPI_DBI_TE_NO_EDGE 0x0