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lines changed Original file line number Diff line number Diff line change @@ -549,17 +549,13 @@ static int fpga_ice40_init(const struct device *dev)
549549
550550#define FPGA_ICE40_BUS_FREQ (inst ) DT_INST_PROP(inst, spi_max_frequency)
551551
552- #define FPGA_ICE40_CONFIG_DELAY_US (inst ) \
553- DT_INST_PROP_OR(inst, config_delay_us, FPGA_ICE40_CONFIG_DELAY_US_MIN)
552+ #define FPGA_ICE40_CONFIG_DELAY_US (inst ) DT_INST_PROP(inst, config_delay_us)
554553
555- #define FPGA_ICE40_CRESET_DELAY_US (inst ) \
556- DT_INST_PROP_OR(inst, creset_delay_us, FPGA_ICE40_CRESET_DELAY_US_MIN)
554+ #define FPGA_ICE40_CRESET_DELAY_US (inst ) DT_INST_PROP(inst, creset_delay_us)
557555
558- #define FPGA_ICE40_LEADING_CLOCKS (inst ) \
559- DT_INST_PROP_OR(inst, leading_clocks, FPGA_ICE40_LEADING_CLOCKS_MIN)
556+ #define FPGA_ICE40_LEADING_CLOCKS (inst ) DT_INST_PROP(inst, leading_clocks)
560557
561- #define FPGA_ICE40_TRAILING_CLOCKS (inst ) \
562- DT_INST_PROP_OR(inst, trailing_clocks, FPGA_ICE40_TRAILING_CLOCKS_MIN)
558+ #define FPGA_ICE40_TRAILING_CLOCKS (inst ) DT_INST_PROP(inst, trailing_clocks)
563559
564560#define FPGA_ICE40_MHZ_DELAY_COUNT (inst ) DT_INST_PROP_OR(inst, mhz_delay_count, 0)
565561
Original file line number Diff line number Diff line change @@ -69,25 +69,26 @@ properties:
6969 mhz-delay-count = <0>;
7070 creset-delay-us :
7171 type : int
72+ default : 1
7273 description : |
7374 Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B.
74- Example usage / default:
75- creset-delay-us = <1>;
75+ The datasheet specifies a minimum of 200ns, therefore the default is set
76+ to 1us.
7677 config-delay-us :
7778 type : int
79+ default : 1200
7880 description : |
7981 Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory.
80- Example usage / default:
81- config-delay-us = <1200>;
82+ The datasheet specifies a minimum of 1200us, which is the default.
8283 leading-clocks :
8384 type : int
85+ default : 8
8486 description : |
8587 Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high.
86- Example usage / default:
87- leading-clocks = <8>;
88+ The datasheet specifies 8 dummy cycles, which is the default.
8889 trailing-clocks :
8990 type : int
91+ default : 49
9092 description : |
9193 After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high.
92- Example usage / default:
93- trailing-clocks = <49>;
94+ The datasheet specifies 49 dummy cycles, which is the default.
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