@@ -275,17 +275,6 @@ static void i2c_stm32_disable_transfer_interrupts(const struct device *dev)
275275 }
276276}
277277
278- static void i2c_stm32_enable_transfer_interrupts (const struct device * dev )
279- {
280- const struct i2c_stm32_config * cfg = dev -> config ;
281- I2C_TypeDef * i2c = cfg -> i2c ;
282-
283- LL_I2C_EnableIT_STOP (i2c );
284- LL_I2C_EnableIT_NACK (i2c );
285- LL_I2C_EnableIT_TC (i2c );
286- LL_I2C_EnableIT_ERR (i2c );
287- }
288-
289278static void i2c_stm32_master_mode_end (const struct device * dev )
290279{
291280 const struct i2c_stm32_config * cfg = dev -> config ;
@@ -413,7 +402,10 @@ static void i2c_stm32_slave_event(const struct device *dev)
413402 }
414403 }
415404
416- i2c_stm32_enable_transfer_interrupts (dev );
405+ LL_I2C_EnableIT_STOP (i2c );
406+ LL_I2C_EnableIT_NACK (i2c );
407+ LL_I2C_EnableIT_TC (i2c );
408+ LL_I2C_EnableIT_ERR (i2c );
417409 }
418410}
419411
@@ -708,137 +700,6 @@ int i2c_stm32_error(const struct device *dev)
708700 return - EIO ;
709701}
710702
711- static int i2c_stm32_msg_write (const struct device * dev , struct i2c_msg * msg ,
712- uint8_t * next_msg_flags , uint16_t slave )
713- {
714- const struct i2c_stm32_config * cfg = dev -> config ;
715- struct i2c_stm32_data * data = dev -> data ;
716- I2C_TypeDef * i2c = cfg -> i2c ;
717- bool is_timeout = false;
718-
719- data -> current .len = msg -> len ;
720- data -> current .buf = msg -> buf ;
721- data -> current .is_write = 1U ;
722- data -> current .is_nack = 0U ;
723- data -> current .is_err = 0U ;
724- data -> current .msg = msg ;
725-
726- #if defined(CONFIG_I2C_STM32_V2_DMA )
727- if (!stm32_buf_in_nocache ((uintptr_t )msg -> buf , msg -> len )) {
728- LOG_DBG ("Tx buffer at %p (len %zu) is in cached memory; cleaning cache" , msg -> buf ,
729- msg -> len );
730- sys_cache_data_flush_range ((void * )msg -> buf , msg -> len );
731- }
732- #endif /* CONFIG_I2C_STM32_V2_DMA */
733-
734- msg_init (dev , msg , next_msg_flags , slave , LL_I2C_REQUEST_WRITE );
735-
736- i2c_stm32_enable_transfer_interrupts (dev );
737- LL_I2C_EnableIT_TX (i2c );
738-
739- if (k_sem_take (& data -> device_sync_sem ,
740- K_MSEC (CONFIG_I2C_STM32_TRANSFER_TIMEOUT_MSEC )) != 0 ) {
741- i2c_stm32_master_mode_end (dev );
742- k_sem_take (& data -> device_sync_sem , K_FOREVER );
743- is_timeout = true;
744- }
745- #ifdef CONFIG_I2C_STM32_V2_DMA
746- dma_finish (dev , msg );
747- #endif
748-
749- if (data -> current .is_nack || data -> current .is_err ||
750- data -> current .is_arlo || is_timeout ) {
751- goto error ;
752- }
753-
754- return 0 ;
755- error :
756- if (data -> current .is_arlo ) {
757- LOG_DBG ("%s: ARLO %d" , __func__ ,
758- data -> current .is_arlo );
759- data -> current .is_arlo = 0U ;
760- }
761-
762- if (data -> current .is_nack ) {
763- LOG_DBG ("%s: NACK" , __func__ );
764- data -> current .is_nack = 0U ;
765- }
766-
767- if (data -> current .is_err ) {
768- LOG_DBG ("%s: ERR %d" , __func__ ,
769- data -> current .is_err );
770- data -> current .is_err = 0U ;
771- }
772-
773- if (is_timeout ) {
774- LOG_DBG ("%s: TIMEOUT" , __func__ );
775- }
776-
777- return - EIO ;
778- }
779-
780- static int i2c_stm32_msg_read (const struct device * dev , struct i2c_msg * msg ,
781- uint8_t * next_msg_flags , uint16_t slave )
782- {
783- const struct i2c_stm32_config * cfg = dev -> config ;
784- struct i2c_stm32_data * data = dev -> data ;
785- I2C_TypeDef * i2c = cfg -> i2c ;
786- bool is_timeout = false;
787-
788- data -> current .len = msg -> len ;
789- data -> current .buf = msg -> buf ;
790- data -> current .is_write = 0U ;
791- data -> current .is_arlo = 0U ;
792- data -> current .is_err = 0U ;
793- data -> current .is_nack = 0U ;
794- data -> current .msg = msg ;
795-
796- msg_init (dev , msg , next_msg_flags , slave , LL_I2C_REQUEST_READ );
797-
798- i2c_stm32_enable_transfer_interrupts (dev );
799- LL_I2C_EnableIT_RX (i2c );
800-
801- if (k_sem_take (& data -> device_sync_sem ,
802- K_MSEC (CONFIG_I2C_STM32_TRANSFER_TIMEOUT_MSEC )) != 0 ) {
803- i2c_stm32_master_mode_end (dev );
804- k_sem_take (& data -> device_sync_sem , K_FOREVER );
805- is_timeout = true;
806- }
807- #ifdef CONFIG_I2C_STM32_V2_DMA
808- dma_finish (dev , msg );
809- #endif
810-
811- if (data -> current .is_nack || data -> current .is_err ||
812- data -> current .is_arlo || is_timeout ) {
813- goto error ;
814- }
815-
816- return 0 ;
817- error :
818- if (data -> current .is_arlo ) {
819- LOG_DBG ("%s: ARLO %d" , __func__ ,
820- data -> current .is_arlo );
821- data -> current .is_arlo = 0U ;
822- }
823-
824- if (data -> current .is_nack ) {
825- LOG_DBG ("%s: NACK" , __func__ );
826- data -> current .is_nack = 0U ;
827- }
828-
829- if (data -> current .is_err ) {
830- LOG_DBG ("%s: ERR %d" , __func__ ,
831- data -> current .is_err );
832- data -> current .is_err = 0U ;
833- }
834-
835- if (is_timeout ) {
836- LOG_DBG ("%s: TIMEOUT" , __func__ );
837- }
838-
839- return - EIO ;
840- }
841-
842703static int stm32_i2c_irq_xfer (const struct device * dev , struct i2c_msg * msg ,
843704 uint8_t * next_msg_flags , uint16_t slave )
844705{
@@ -961,11 +822,9 @@ static int stm32_i2c_irq_xfer(const struct device *dev, struct i2c_msg *msg,
961822 /* Enable interrupts */
962823 LL_I2C_WriteReg (regs , CR1 , cr1 );
963824
964- /* Wait for IRQ to complete or timeout
965- * Timeout scales with one millisecond for each byte to
966- * transfer so that slave can do some clock stretching
967- */
968- if (k_sem_take (& data -> device_sync_sem , K_MSEC (msg -> len + 10U )) != 0U ) {
825+ /* Wait for IRQ to complete or timeout */
826+ if (k_sem_take (& data -> device_sync_sem ,
827+ K_MSEC (CONFIG_I2C_STM32_TRANSFER_TIMEOUT_MSEC )) != 0U ) {
969828 is_timeout = true;
970829 }
971830
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