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soc: microblaze: add demo SoC with timer, interrupt_controller and uart
Internal references: FWRIVERHD-5063 Signed-off-by: Alp Sayin <[email protected]>
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‎dts/microblaze/xlnx/microblaze_demo.dtsi‎

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include "mem.h"
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#include "xparam_helper.h"
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/ {
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microblazeclk: microblaze-clock {
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compatible = "fixed-clock";
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clock-frequency = <200000000>;
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#clock-cells = <0>;
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};
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peripheralclk: peripheral-clock {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0 {
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device_type = "cpu";
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compatible = "xlnx,microblaze";
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reg = <0>;
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clock-frequency = <200000000>;
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i-cache-base = <0x00000000>;
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i-cache-size = <0x800>;
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i-cache-line-size = <16>;
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d-cache-base = <0x00000000>;
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d-cache-size = <0x2000>;
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d-cache-line-size = <16>;
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d-cache-use-writeback = <0>;
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};
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};
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ddr0: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_M(256)>;
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};
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soc {
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interrupt-parent = <&intc0>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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intc0: interrupt-controller@fe010000 {
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compatible = "xlnx,intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0xfe010000 DT_SIZE_K(128)>;
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};
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tmrctr0: timer@fe00c000 {
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compatible = "xlnx,tmrctr";
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reg = <0xfe00c000 DT_SIZE_K(4)>;
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interrupts = <15 15>;
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clock-frequency = <50000000>;
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};
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uart0: uart@fe020000 {
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compatible = "xlnx,xps-uartlite-1.00.a";
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reg = <0xfe020000 DT_SIZE_K(64)>;
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interrupts = <14 14>;
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clock-frequency = <50000000>;
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parity = "none";
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status = "disabled";
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};
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};
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};

‎soc/microblaze/microblaze_demo/CMakeLists.txt‎

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(include)
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zephyr_sources(
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soc.c
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)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/microblaze/microblaze_demo/Kconfig‎

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XLNX_MICROBLAZE_DEMO
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select MICROBLAZE
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select XLNX_INTC
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select XLNX_TMRCTR

‎soc/microblaze/microblaze_demo/Kconfig.defconfig‎

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XLNX_MICROBLAZE_DEMO
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 200000000
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config SYS_CLOCK_TICKS_PER_SEC
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default 100
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config NUM_IRQS
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default 32
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endif # SOC_XLNX_MICROBLAZE_DEMO

‎soc/microblaze/microblaze_demo/Kconfig.soc‎

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XLNX_MICROBLAZE_DEMO
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bool
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config SOC
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default "microblaze_demo" if SOC_XLNX_MICROBLAZE_DEMO

‎soc/microblaze/microblaze_demo/include/layout.h‎

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_MICROBLAZE_SOC_INCLUDE_LAYOUT_H_
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#define ZEPHYR_SOC_MICROBLAZE_SOC_INCLUDE_LAYOUT_H_
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#include <zephyr/devicetree.h>
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#define _DDR_NODE DT_CHOSEN(zephyr_sram)
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#define _LAYOUT_DDR_LOC DT_REG_ADDR(_DDR_NODE)
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#define _LAYOUT_DDR_SIZE DT_REG_SIZE(_DDR_NODE)
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#define _RESET_VECTOR (_LAYOUT_DDR_LOC)
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#define _USER_VECTOR (_RESET_VECTOR + 0x8)
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#define _INTR_VECTOR (_RESET_VECTOR + 0x10)
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#define _EXC_VECTOR (_RESET_VECTOR + 0x20)
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#endif /* ZEPHYR_SOC_MICROBLAZE_SOC_INCLUDE_LAYOUT_H_ */

‎soc/microblaze/microblaze_demo/include/soc.h‎

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SOC_H_
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#define __SOC_H_
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#include <stdint.h>
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#include "layout.h"
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#ifdef CONFIG_XLNX_INTC
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extern void xlnx_intc_irq_enable(uint32_t irq);
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extern void xlnx_intc_irq_disable(uint32_t irq);
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extern void xlnx_intc_irq_acknowledge(uint32_t mask);
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extern uint32_t xlnx_intc_irq_pending(void);
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extern uint32_t xlnx_intc_irq_get_enabled(void);
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extern uint32_t xlnx_intc_irq_pending_vector(void);
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#endif /* CONFIG_XLNX_INTC */
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#endif /* __SOC_H_ */

‎soc/microblaze/microblaze_demo/linker.ld‎

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <layout.h>
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_DDR_LOC = _LAYOUT_DDR_LOC;
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_DDR_SIZE = _LAYOUT_DDR_SIZE;
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MEMORY
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{
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app_ram (RX) : ORIGIN = _DDR_LOC, LENGTH = _DDR_SIZE
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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#include <zephyr/arch/microblaze/linker.ld>

‎soc/microblaze/microblaze_demo/soc.c‎

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <[email protected]>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc.h"
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc);
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#ifdef CONFIG_XLNX_INTC
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/**
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* @brief Override arch_irq_enable with a call to Xintc driver
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*
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* @param irq irq number to enable
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*/
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void arch_irq_enable(uint32_t irq)
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{
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xlnx_intc_irq_enable(irq);
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}
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/**
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* @brief Override arch_irq_disable with a call to Xintc driver
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*
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* @param irq irq number to disable
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*/
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void arch_irq_disable(uint32_t irq)
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{
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xlnx_intc_irq_disable(irq);
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}
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/**
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* @brief Override arch_irq_is_enabled with a call to Xintc driver
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*
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* @param irq irq number to see if enabled
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*/
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int arch_irq_is_enabled(unsigned int irq)
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{
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return BIT(irq) & xlnx_intc_irq_get_enabled();
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}
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/**
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* @brief Returns the currently pending interrupts.
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*
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* @return Pending IRQ bitmask. Pending IRQs will have their bitfield set to 1. 0 if no interrupt is
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* pending.
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*/
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uint32_t arch_irq_pending(void)
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{
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return xlnx_intc_irq_pending();
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};
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/**
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* @brief Returns the vector for highest pending interrupt.
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*
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* @return Returns the vector for (i.e. index) for highest-prio/lowest-num pending interrupt to be
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* used in a jump table. This is used used for sw_isr_table.
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*/
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uint32_t arch_irq_pending_vector(uint32_t ipending)
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{
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ARG_UNUSED(ipending);
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return xlnx_intc_irq_pending_vector();
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}
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#endif /* #ifdef CONFIG_XLNX_INTC */
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* @return 0
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*/
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static int soc_init(void)
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{
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

‎soc/microblaze/microblaze_demo/soc.yml‎

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socs:
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- name: microblaze_demo

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