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yboutreuxgalak
yboutreux
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gpio: Add stm32mp157c_dk2 board support
Add support for stm32mp1x GPIO with Zephyr GPIO driver Signed-off-by: Yaël Boutreux <[email protected]> Signed-off-by: Arnaud Pouliquen <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
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‎boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst‎

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@@ -168,6 +168,8 @@ features:
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig``

‎boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml‎

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@@ -6,6 +6,8 @@ toolchain:
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- zephyr
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- gccarmemb
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- xtools
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supported:
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- gpio
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testing:
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ignore_tags:
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- cmsis_rtos_v2
@@ -17,7 +19,6 @@ testing:
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- cmm
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- shell
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- LED
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- gpio
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- nfc
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ram: 256
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flash: 64

‎boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig‎

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@@ -6,6 +6,9 @@ CONFIG_CORTEX_M_SYSTICK=y
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# 209 MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=209000000
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# enable GPIO
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CONFIG_GPIO=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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‎drivers/gpio/gpio_stm32.c‎

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@@ -214,6 +214,8 @@ const int gpio_stm32_enable_int(int port, int pin)
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#if defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X)
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line = ((pin % 4 * 4) << 16) | (pin / 4);
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#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
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line = (((pin * 8) % 32) << 16) | (pin / 4);
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#else
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line = (0xF << ((pin % 4 * 4) + 16)) | (pin / 4);
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#endif
@@ -231,6 +233,8 @@ const int gpio_stm32_enable_int(int port, int pin)
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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LL_GPIO_AF_SetEXTISource(port, line);
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#elif CONFIG_SOC_SERIES_STM32MP1X
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LL_EXTI_SetEXTISource(port, line);
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#else
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LL_SYSCFG_SetEXTISource(port, line);
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#endif

‎drivers/gpio/gpio_stm32.h‎

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@@ -112,6 +112,19 @@
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#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
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#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
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#define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
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#elif CONFIG_SOC_SERIES_STM32MP1X
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#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
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#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
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#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
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#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
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#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
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#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
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#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
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#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
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#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
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#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
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#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
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#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
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#elif CONFIG_SOC_SERIES_STM32WBX
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#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
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#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA

‎dts/arm/st/mp1/stm32mp157.dtsi‎

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@@ -6,6 +6,8 @@
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#include <mem.h>
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
@@ -39,6 +41,111 @@
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label = "STM32_CLK_RCC";
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};
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pinctrl: pin-controller@50002000 {
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compatible = "st,stm32-pinmux";
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reg = <0x50002000 0x9000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@50002000 {
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compatible = "st,stm32-gpio";
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reg = <0x50002000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@50003000 {
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compatible = "st,stm32-gpio";
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reg = <0x50003000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@50004000 {
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compatible = "st,stm32-gpio";
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reg = <0x50004000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
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label = "GPIOC";
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};
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gpiod: gpio@50005000 {
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compatible = "st,stm32-gpio";
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reg = <0x50005000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@50006000 {
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compatible = "st,stm32-gpio";
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reg = <0x50006000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@50007000 {
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compatible = "st,stm32-gpio";
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reg = <0x50007000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@50008000 {
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compatible = "st,stm32-gpio";
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reg = <0x50008000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
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label = "GPIOG";
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};
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gpioh: gpio@50009000 {
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compatible = "st,stm32-gpio";
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reg = <0x50009000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
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label = "GPIOH";
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};
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gpioi: gpio@5000a000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000a000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
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label = "GPIOI";
129+
};
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gpioj: gpio@5000b000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000b000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
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label = "GPIOJ";
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};
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140+
gpiok: gpio@5000c000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000c000 0x400>;
143+
gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
146+
label = "GPIOK";
147+
};
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};
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};
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};
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‎soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series‎

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@@ -16,4 +16,32 @@ config STM32_CORE_CM4
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bool "define stm32 core"
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default y
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if GPIO_STM32
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21+
config GPIO_STM32_PORTD
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default y
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config GPIO_STM32_PORTE
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default y
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config GPIO_STM32_PORTF
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default y
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config GPIO_STM32_PORTG
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default y
32+
33+
config GPIO_STM32_PORTH
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default y
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36+
config GPIO_STM32_PORTI
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default y
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config GPIO_STM32_PORTJ
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default y
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config GPIO_STM32_PORTK
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default y
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endif # GPIO_STM32
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endif # SOC_SERIES_STM32MP1X

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