soc: st: stm32: use CONFIG_STM32_FLASH_PREFETCH where applicable

etienne-lms · jhedberg · commit b56487892d71 · 2025-10-03T12:50:47.000+03:00
Use CONFIG_STM32_FLASH_PREFETCH config option to enable flash prefetch
in C0/F0/F1/F2/F3/F4/F7/G4/L0/L1/L4/U0/U3/WB/WBA/WBL for consistency
with other SoCs that use this configuration switch, default enabled
at SoC default config level.

Add SoC hidden config option HAS_STM32_FLASH_PREFETCH enabled for
SoCs that support the feature. STM32_FLASH_PREFETCH is default
enabled for all SoC that have HAS_STM32_FLASH_PREFETCH unless target
specific constraints (as for G0Bx/G0Cx SoCs).

Signed-off-by: Etienne Carriere &lt;etienne.carriere@st.com&gt;
diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig
@@ -55,8 +55,19 @@ config SWJ_ANALOG_PRIORITY
 	  This priority must be greater than GPIO_INIT_PRIORITY and lower than
 	  UART_INIT_PRIORITY.
 
+config HAS_STM32_FLASH_PREFETCH
+	bool
+	help
+	  Hidden symbol selected by SoCs which support flash prefetch.
+
 config STM32_FLASH_PREFETCH
 	bool "Flash prefetch buffer"
+	default y
+	depends on HAS_STM32_FLASH_PREFETCH
+	help
+	  Enable flash prefetch. For power efficiency, it is recommended to
+	  be enabled when flash is accessed through a cache memory. Flash
+	  prefetch also improves performances a bit.
 
 config STM32_WKUP_PINS
 	bool "STM32 PWR Wake-up Pins"
diff --git a/soc/st/stm32/stm32c0x/Kconfig b/soc/st/stm32/stm32c0x/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_STM32C0X
 	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_HAS_ARM_MPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_PM
 	select HAS_POWEROFF
diff --git a/soc/st/stm32/stm32c0x/soc.c b/soc/st/stm32/stm32c0x/soc.c
@@ -28,7 +28,9 @@ void soc_early_init_hook(void)
 {
 	/* Enable ART Accelerator I-cache and prefetch */
 	LL_FLASH_EnableInstCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 48 MHz from HSI */
diff --git a/soc/st/stm32/stm32f0x/Kconfig b/soc/st/stm32/stm32f0x/Kconfig
@@ -9,4 +9,5 @@ config SOC_SERIES_STM32F0X
 	select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32f0x/soc.c b/soc/st/stm32/stm32f0x/soc.c
@@ -64,8 +64,10 @@ void relocate_vector_table(void)
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
diff --git a/soc/st/stm32/stm32f1x/Kconfig b/soc/st/stm32/stm32f1x/Kconfig
@@ -8,6 +8,7 @@ config SOC_SERIES_STM32F1X
 	select CPU_CORTEX_M3
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select HAS_PM
 	select HAS_POWEROFF
 	select HAS_SWO
diff --git a/soc/st/stm32/stm32f1x/soc.c b/soc/st/stm32/stm32f1x/soc.c
@@ -24,7 +24,7 @@
  */
 void soc_early_init_hook(void)
 {
-#ifdef FLASH_ACR_PRFTBE
+#if defined(FLASH_ACR_PRFTBE) && defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
 #endif
diff --git a/soc/st/stm32/stm32f2x/Kconfig b/soc/st/stm32/stm32f2x/Kconfig
@@ -8,6 +8,7 @@ config SOC_SERIES_STM32F2X
 	select CPU_CORTEX_M3
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select HAS_SWO
 	select CPU_HAS_ARM_MPU
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32f2x/soc.c b/soc/st/stm32/stm32f2x/soc.c
@@ -29,7 +29,9 @@ void soc_early_init_hook(void)
 	/* Enable ART Flash I/D-cache accelerator and prefetch */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
diff --git a/soc/st/stm32/stm32f3x/Kconfig b/soc/st/stm32/stm32f3x/Kconfig
@@ -9,5 +9,6 @@ config SOC_SERIES_STM32F3X
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select HAS_SWO
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32f3x/soc.c b/soc/st/stm32/stm32f3x/soc.c
@@ -22,8 +22,10 @@
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 8 MHz from HSI */
diff --git a/soc/st/stm32/stm32f4x/Kconfig b/soc/st/stm32/stm32f4x/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_STM32F4X
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_PM
diff --git a/soc/st/stm32/stm32f4x/soc.c b/soc/st/stm32/stm32f4x/soc.c
@@ -26,7 +26,9 @@ extern void stm32_power_init(void);
 void soc_early_init_hook(void)
 {
 	/* Enable ART Flash I/D-cache and prefetch */
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
 
diff --git a/soc/st/stm32/stm32f7x/Kconfig b/soc/st/stm32/stm32f7x/Kconfig
@@ -11,6 +11,7 @@ config SOC_SERIES_STM32F7X
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32f7x/soc.c b/soc/st/stm32/stm32f7x/soc.c
@@ -27,7 +27,9 @@ void soc_early_init_hook(void)
 {
 	/* Enable ART Flash cache accelerator and prefetch */
 	LL_FLASH_EnableART();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	sys_cache_instr_enable();
 	sys_cache_data_enable();
diff --git a/soc/st/stm32/stm32g0x/Kconfig b/soc/st/stm32/stm32g0x/Kconfig
@@ -10,6 +10,7 @@ config SOC_SERIES_STM32G0X
 	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_HAS_ARM_MPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_PM
 	select HAS_POWEROFF
diff --git a/soc/st/stm32/stm32g0x/Kconfig.defconfig b/soc/st/stm32/stm32g0x/Kconfig.defconfig
@@ -49,12 +49,12 @@ config SHARED_INTERRUPTS
 
 endif # UART_STM32
 
-# Default enable flash prefetch for all G0xx SoCs but G0Bx, G0Cx since ErrataSheet
-# ES0548/ES0549, section "Prefetch failure when branching across flash memory banks
+# Default disable flash prefetch for G0Bx and G0Cx since ErrataSheet ES0548/ES0549,
+# section "Prefetch failure when branching across flash memory banks
 # which causes code execution corruption and may lead to HardFault interrupt"
 # Project may override this configuration if sure no cross-bank prefetch access is
 # awaited.
 config STM32_FLASH_PREFETCH
-	default y if !SOC_STM32G0B0XX && !SOC_STM32G0B1XX && !SOC_STM32G0C1XX
+	default n if SOC_STM32G0B0XX || SOC_STM32G0B1XX || SOC_STM32G0C1XX
 
 endif # SOC_SERIES_STM32G0X
diff --git a/soc/st/stm32/stm32g4x/Kconfig b/soc/st/stm32/stm32g4x/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_STM32G4X
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_PM
 	select HAS_SWO
diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c
@@ -32,7 +32,9 @@ void soc_early_init_hook(void)
 	/* Enable ART Accelerator I/D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
diff --git a/soc/st/stm32/stm32l0x/Kconfig b/soc/st/stm32/stm32l0x/Kconfig
@@ -8,6 +8,7 @@ config SOC_SERIES_STM32L0X
 	select CPU_CORTEX_M0PLUS
 	select CPU_CORTEX_M_HAS_VTOR
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select HAS_PM
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32l0x/soc.c b/soc/st/stm32/stm32l0x/soc.c
@@ -25,8 +25,10 @@
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 2.1 MHz from MSI */
diff --git a/soc/st/stm32/stm32l1x/Kconfig b/soc/st/stm32/stm32l1x/Kconfig
@@ -11,5 +11,6 @@ config SOC_SERIES_STM32L1X
 	select HAS_PM
 	select HAS_POWEROFF
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select HAS_SWO
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32l1x/soc.c b/soc/st/stm32/stm32l1x/soc.c
@@ -26,8 +26,10 @@
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 2.1 MHz from MSI */
diff --git a/soc/st/stm32/stm32l4x/Kconfig b/soc/st/stm32/stm32l4x/Kconfig
@@ -10,6 +10,7 @@ config SOC_SERIES_STM32L4X
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_PM
diff --git a/soc/st/stm32/stm32l4x/soc.c b/soc/st/stm32/stm32l4x/soc.c
@@ -31,7 +31,9 @@ void soc_early_init_hook(void)
 	/* Enable the ART Accelerator I-cache, D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
diff --git a/soc/st/stm32/stm32u0x/Kconfig b/soc/st/stm32/stm32u0x/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_STM32U0X
 	select CPU_HAS_ARM_MPU
 	select CPU_CORTEX_M_HAS_VTOR
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select SOC_EARLY_INIT_HOOK
 	select HAS_PM
diff --git a/soc/st/stm32/stm32u0x/soc.c b/soc/st/stm32/stm32u0x/soc.c
@@ -27,8 +27,10 @@ LOG_MODULE_REGISTER(soc);
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART Accelerator prefetch */
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 16 MHz from HSI */
diff --git a/soc/st/stm32/stm32u3x/Kconfig b/soc/st/stm32/stm32u3x/Kconfig
@@ -12,4 +12,5 @@ config SOC_SERIES_STM32U3X
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32u3x/soc.c b/soc/st/stm32/stm32u3x/soc.c
@@ -28,8 +28,10 @@ LOG_MODULE_REGISTER(soc);
  */
 void soc_early_init_hook(void)
 {
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	/* Enable ART Accelerator prefetch */
 	__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
 
 	sys_cache_instr_enable();
 
diff --git a/soc/st/stm32/stm32wbax/Kconfig b/soc/st/stm32/stm32wbax/Kconfig
@@ -13,6 +13,7 @@ config SOC_SERIES_STM32WBAX
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select USE_STM32_HAL_PWR_EX
 	select USE_STM32_HAL_CORTEX
 	select HAS_PM
diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig b/soc/st/stm32/stm32wbax/Kconfig.defconfig
@@ -20,9 +20,6 @@ endchoice
 config STM32_LPTIM_TIMER
 	default y if PM
 
-config STM32_FLASH_PREFETCH
-	default y
-
 config BT_STM32WBA
 	select DYNAMIC_INTERRUPTS
 	select DYNAMIC_DIRECT_INTERRUPTS
diff --git a/soc/st/stm32/stm32wbx/Kconfig b/soc/st/stm32/stm32wbx/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_STM32WBX
 	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_FPU
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_PM
diff --git a/soc/st/stm32/stm32wbx/soc.c b/soc/st/stm32/stm32wbx/soc.c
@@ -31,7 +31,9 @@ void soc_early_init_hook(void)
 	/* Enable the ART Accelerator I-cache, D-cache and prefetch */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
diff --git a/soc/st/stm32/stm32wlx/Kconfig b/soc/st/stm32/stm32wlx/Kconfig
@@ -8,6 +8,7 @@ config SOC_SERIES_STM32WLX
 	select CPU_CORTEX_M4
 	select CPU_CORTEX_M_HAS_DWT
 	select HAS_STM32CUBE
+	select HAS_STM32_FLASH_PREFETCH
 	select CPU_HAS_ARM_MPU
 	select HAS_PM
 	select HAS_POWEROFF
diff --git a/soc/st/stm32/stm32wlx/soc.c b/soc/st/stm32/stm32wlx/soc.c
@@ -32,7 +32,9 @@ void soc_early_init_hook(void)
 	/* Enable CPU data and instruction cache and prefetch */
 	LL_FLASH_EnableInstCache();
 	LL_FLASH_EnableDataCache();
+#if defined(CONFIG_STM32_FLASH_PREFETCH)
 	LL_FLASH_EnablePrefetch();
+#endif
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */

Original file line number	Diff line number	Diff line change
`@@ -28,7 +28,9 @@ void soc_early_init_hook(void)`
`28`	`28`	`{`
`29`	`29`	`/* Enable ART Accelerator I-cache and prefetch */`
`30`	`30`	`LL_FLASH_EnableInstCache();`
	`31`	`+#if defined(CONFIG_STM32_FLASH_PREFETCH)`
`31`	`32`	`LL_FLASH_EnablePrefetch();`
	`33`	`+#endif`
`32`	`34`
`33`	`35`	`/* Update CMSIS SystemCoreClock variable (HCLK) */`
`34`	`36`	`/* At reset, system core clock is set to 48 MHz from HSI */`
Original file line number	Diff line number	Diff line change
`@@ -24,7 +24,7 @@`
`24`	`24`	`*/`
`25`	`25`	`void soc_early_init_hook(void)`
`26`	`26`	`{`
`27`		`-#ifdef FLASH_ACR_PRFTBE`
	`27`	`+#if defined(FLASH_ACR_PRFTBE) && defined(CONFIG_STM32_FLASH_PREFETCH)`
`28`	`28`	`/* Enable ART Accelerator prefetch */`
`29`	`29`	`LL_FLASH_EnablePrefetch();`
`30`	`30`	`#endif`