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tests/drivers/clock_control: stm32u5: Add a _devices test
Add a stm32u5_devices test which aims at testing devices clock control configuration on stm32u5 targets Signed-off-by: Erwan Gouriou <[email protected]>
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‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(stm32_clock_configuration_u5_devices)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/core_init.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay clears clocks back to a state equivalent to what could
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* be found in stm32h7.dtsi
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ clock-frequency;
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/delete-property/ hse-bypass;
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};
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&clk_hsi {
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status = "disabled";
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};
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&clk_lse {
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status = "disabled";
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};
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&clk_msis {
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status = "disabled";
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/delete-property/ msi-range;
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/delete-property/ msi-pll-mode;
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};
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&clk_msik {
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status = "disabled";
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/delete-property/ msi-range;
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/delete-property/ msi-pll-mode;
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};
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&pll1 {
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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/delete-property/ ahb-prescaler;
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/delete-property/ apb1-prescaler;
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/delete-property/ apb2-prescaler;
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/delete-property/ apb3-prescaler;
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};
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&spi1 {
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pinctrl-0 = <&spi1_nss_pe12 &spi1_sck_pe13
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&spi1_miso_pe14 &spi1_mosi_pe15>;
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pinctrl-names = "default";
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status = "disabled";
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_lse {
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status = "okay";
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};
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&clk_msis {
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status = "okay";
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msi-range = <4>;
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msi-pll-mode;
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};
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&pll1 {
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div-m = <1>;
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mul-n = <80>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_msis>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll1>;
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clock-frequency = <DT_FREQ_M(160)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <1>;
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apb2-prescaler = <1>;
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apb3-prescaler = <1>;
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_hsi_16.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay performs configuration from clean sheet.
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* It is assumed that it is applied after core_init.overlay file.
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*/
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&clk_hsi {
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status = "okay";
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};
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&spi1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
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<&rcc STM32_SRC_HSI16 SPI1_SEL(2)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_msik.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay performs configuration from clean sheet.
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* It is assumed that it is applied after core_init.overlay file.
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*/
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&clk_msik {
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msi-range = <4>;
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status = "okay";
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};
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&spi1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
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<&rcc STM32_SRC_MSIK SPI1_SEL(3)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_pclk2.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay performs configuration from clean sheet.
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* It is assumed that it is applied after core_init.overlay file.
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*/
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&spi1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/spi1_sysclk.overlay‎

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/*
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay performs configuration from clean sheet.
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* It is assumed that it is applied after core_init.overlay file.
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*/
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&spi1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
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<&rcc STM32_SRC_SYSCLK SPI1_SEL(1)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/prj.conf‎

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CONFIG_ZTEST=y

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ztest.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(test);
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#define DT_DRV_COMPAT st_stm32_spi
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#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT
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#define STM32_SPI_OPT_CLOCK_SUPPORT 1
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#else
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#define STM32_SPI_OPT_CLOCK_SUPPORT 0
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#endif
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#define DT_NO_CLOCK 0xFFFFU
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/* Not device related, but keep it to ensure core clock config is correct */
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static void test_sysclk_freq(void)
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{
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uint32_t soc_sys_clk_freq;
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soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
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zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
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"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
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}
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static void test_spi_clk_config(void)
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{
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static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(spi1);
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uint32_t spi1_actual_clk_src;
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uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq;
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int r;
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/* Test clock_on(reg_clk) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable SPI gating clock");
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zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on");
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TC_PRINT("SPI1 gating clock on\n");
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if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) {
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/* Test clock_on(alt source) */
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r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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NULL);
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zassert_true((r == 0), "Could not configure SPI source clk");
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TC_PRINT("SPI1 clk source configured\n");
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/* Test clk source */
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spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE();
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if (pclken[1].bus == STM32_SRC_HSI16) {
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zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_HSI,
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"Expected SPI src: HSI (%d). Actual SPI src: %d",
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RCC_SPI1CLKSOURCE_HSI, spi1_actual_clk_src);
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} else if (pclken[1].bus == STM32_SRC_SYSCLK) {
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zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_SYSCLK,
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"Expected SPI src: SYSCLK (%d). Actual SPI src: %d",
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RCC_SPI1CLKSOURCE_SYSCLK, spi1_actual_clk_src);
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} else {
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zassert_true(1, "Unexpected clk src(%d)", spi1_actual_clk_src);
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}
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/* Test get_rate(source clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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&spi1_dt_clk_freq);
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zassert_true((r == 0), "Could not get SPI clk freq");
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spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
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zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq,
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"Expected SPI clk: (%d). Actual SPI clk: %d",
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spi1_dt_clk_freq, spi1_actual_clk_freq);
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} else {
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/* No alt clock available, get rate from gating clock */
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/* Test get_rate(gating clock) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0],
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&spi1_dt_clk_freq);
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zassert_true((r == 0), "Could not get SPI pclk freq");
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spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
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zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq,
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"Expected SPI clk: (%d). Actual SPI clk: %d",
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spi1_dt_clk_freq, spi1_actual_clk_freq);
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}
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/* Test clock_off(gating clock) */
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r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not disable SPI reg_clk");
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zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off");
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TC_PRINT("SPI1 gating clock off\n");
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/* Test clock_off(source clk) */
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/* Not supported today */
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}
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void test_main(void)
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{
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ztest_test_suite(test_stm32u5_devices_clocks,
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ztest_unit_test(test_sysclk_freq),
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ztest_unit_test(test_spi_clk_config)
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);
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ztest_run_test_suite(test_stm32u5_devices_clocks);
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}

‎tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/testcase.yaml‎

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common:
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timeout: 5
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platform_allow: b_u585i_iot02a
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tests:
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drivers.stm32_clock_configuration.dev_u5.spi1_pclk2:
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extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pclk2.overlay"
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drivers.stm32_clock_configuration.dev_u5.spi1_hsi_16:
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extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_hsi_16.overlay"
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drivers.stm32_clock_configuration.dev_u5.spi1_msik:
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extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_msik.overlay"
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drivers.stm32_clock_configuration.dev_u5.spi1_sysclk:
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extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_sysclk.overlay"

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