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gautierg-stcarlescufi
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carlescufi
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drivers: adc: make use of new stm32 adc compatibles
Several sections of the STM32 ADC driver are #ifdef by a combination of the same SOC defines that share similar IPs. These are F2/F4/F7/L1, and F1/F37x. Each of these combinations is now replaced by a specific compatible, which makes the code a bit lighter and more succinct. Signed-off-by: Guillaume Gautier <[email protected]>
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‎drivers/adc/adc_stm32.c

Lines changed: 30 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@ LOG_MODULE_REGISTER(adc_stm32);
5757
* ADC_VER_V5_V90 -> STM32H72x/H73x
5858
* ADC_VER_V5_X -> STM32H74x/H75x && U5
5959
* ADC_VER_V5_3 -> STM32H7Ax/H7Bx
60+
* compat st_stm32f1_adc -> STM32F1, F37x (ADC1_V2_5)
61+
* compat st_stm32f4_adc -> STM32F2, F4, F7, L1
6062
*/
6163

6264
#define ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(value) \
@@ -308,20 +310,14 @@ static void adc_stm32_start_conversion(const struct device *dev)
308310
LOG_DBG("Starting conversion");
309311

310312
#if !defined(CONFIG_SOC_SERIES_STM32F1X) && \
311-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
312-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
313-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
314-
!defined(CONFIG_SOC_SERIES_STM32L1X)
313+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
315314
LL_ADC_REG_StartConversion(adc);
316315
#else
317316
LL_ADC_REG_StartConversionSWStart(adc);
318317
#endif
319318
}
320319

321-
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
322-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
323-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
324-
!defined(CONFIG_SOC_SERIES_STM32L1X)
320+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
325321

326322
/* Number of ADC clock cycles to wait before of after starting calibration */
327323
#if defined(LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES)
@@ -375,8 +371,7 @@ static void adc_stm32_calib(const struct device *dev)
375371
LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
376372
#elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
377373
defined(CONFIG_SOC_SERIES_STM32F0X) || \
378-
defined(CONFIG_SOC_SERIES_STM32F1X) || \
379-
defined(STM32F3X_ADC_V2_5) || \
374+
DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
380375
defined(CONFIG_SOC_SERIES_STM32G0X) || \
381376
defined(CONFIG_SOC_SERIES_STM32L0X) || \
382377
defined(CONFIG_SOC_SERIES_STM32WLX)
@@ -408,12 +403,8 @@ static void adc_stm32_disable(ADC_TypeDef *adc)
408403
* the ADC is completely stopped.
409404
*/
410405

411-
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
412-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
413-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
414-
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
415-
!defined(STM32F3X_ADC_V2_5) && \
416-
!defined(CONFIG_SOC_SERIES_STM32L1X)
406+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
407+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
417408
if (LL_ADC_REG_IsConversionOngoing(adc)) {
418409
LL_ADC_REG_StopConversion(adc);
419410
while (LL_ADC_REG_IsConversionOngoing(adc)) {
@@ -423,14 +414,10 @@ static void adc_stm32_disable(ADC_TypeDef *adc)
423414

424415
#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \
425416
!defined(CONFIG_SOC_SERIES_STM32F0X) && \
426-
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
427-
!defined(STM32F3X_ADC_V2_5) && \
428-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
429-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
430-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
417+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
418+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \
431419
!defined(CONFIG_SOC_SERIES_STM32G0X) && \
432420
!defined(CONFIG_SOC_SERIES_STM32L0X) && \
433-
!defined(CONFIG_SOC_SERIES_STM32L1X) && \
434421
!defined(CONFIG_SOC_SERIES_STM32WLX)
435422
if (LL_ADC_INJ_IsConversionOngoing(adc)) {
436423
LL_ADC_INJ_StopConversion(adc);
@@ -450,11 +437,8 @@ static void adc_stm32_disable(ADC_TypeDef *adc)
450437

451438
#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
452439
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
453-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
454440
!defined(CONFIG_SOC_SERIES_STM32F3X) && \
455-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
456-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
457-
!defined(CONFIG_SOC_SERIES_STM32L1X)
441+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
458442

459443
#ifdef LL_ADC_OVS_RATIO_2
460444
/* table for shifting oversampling mostly for ADC3 != ADC_VER_V5_V90 */
@@ -560,12 +544,8 @@ static int adc_stm32_enable(ADC_TypeDef *adc)
560544
return 0;
561545
}
562546

563-
#if !defined(STM32F3X_ADC_V2_5) && \
564-
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
565-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
566-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
567-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
568-
!defined(CONFIG_SOC_SERIES_STM32L1X)
547+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
548+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
569549
LL_ADC_ClearFlag_ADRDY(adc);
570550
LL_ADC_Enable(adc);
571551

@@ -700,11 +680,11 @@ static void dma_callback(const struct device *dev, void *user_data,
700680
LOG_DBG("dma callback");
701681

702682
if (channel == data->dma.channel) {
703-
#if !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5)
683+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
704684
if (LL_ADC_IsActiveFlag_OVR(adc) || (status >= 0)) {
705685
#else
706686
if (status >= 0) {
707-
#endif /* !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5) */
687+
#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
708688
data->samples_count = data->channel_count;
709689
data->buffer += data->channel_count;
710690
/* Stop the DMA engine, only to start it again when the callback returns
@@ -713,9 +693,9 @@ static void dma_callback(const struct device *dev, void *user_data,
713693
* within adc_context_start_sampling
714694
*/
715695
dma_stop(data->dma.dma_dev, data->dma.channel);
716-
#if !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5)
696+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
717697
LL_ADC_ClearFlag_OVR(adc);
718-
#endif /* !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5) */
698+
#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
719699
/* No need to invalidate the cache because it's assumed that
720700
* the address is in a non-cacheable SRAM region.
721701
*/
@@ -926,11 +906,8 @@ static int start_read(const struct device *dev,
926906

927907
#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
928908
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
929-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
930909
!defined(CONFIG_SOC_SERIES_STM32F3X) && \
931-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
932-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
933-
!defined(CONFIG_SOC_SERIES_STM32L1X)
910+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
934911

935912
switch (sequence->oversampling) {
936913
case 0:
@@ -982,12 +959,8 @@ static int start_read(const struct device *dev,
982959
#endif
983960

984961
if (sequence->calibrate) {
985-
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
986-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
987-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
988-
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
989-
!defined(STM32F3X_ADC_V2_5) && \
990-
!defined(CONFIG_SOC_SERIES_STM32L1X)
962+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
963+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
991964

992965
/* we cannot calibrate the ADC while the ADC is enabled */
993966
adc_stm32_disable(adc);
@@ -1005,18 +978,14 @@ static int start_read(const struct device *dev,
1005978
*/
1006979
adc_stm32_enable(adc);
1007980

1008-
#if !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5)
981+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1009982
LL_ADC_ClearFlag_OVR(adc);
1010-
#endif /* !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5) */
983+
#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
1011984

1012985
#if !defined(CONFIG_ADC_STM32_DMA)
1013-
#if defined(CONFIG_SOC_SERIES_STM32F2X) || \
1014-
defined(CONFIG_SOC_SERIES_STM32F4X) || \
1015-
defined(CONFIG_SOC_SERIES_STM32F7X) || \
1016-
defined(CONFIG_SOC_SERIES_STM32L1X)
986+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
1017987
LL_ADC_EnableIT_EOCS(adc);
1018-
#elif defined(STM32F3X_ADC_V2_5) || \
1019-
defined(CONFIG_SOC_SERIES_STM32F1X)
988+
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
1020989
LL_ADC_EnableIT_EOS(adc);
1021990
#else
1022991
LL_ADC_EnableIT_EOC(adc);
@@ -1321,12 +1290,8 @@ static int adc_stm32_init(const struct device *dev)
13211290
* any enable or calibration actions.
13221291
*/
13231292
#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
1324-
!defined(CONFIG_SOC_SERIES_STM32F1X) && \
1325-
!defined(CONFIG_SOC_SERIES_STM32F2X) && \
1326-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
1327-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
1328-
!defined(STM32F3X_ADC_V2_5) && \
1329-
!defined(CONFIG_SOC_SERIES_STM32L1X)
1293+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
1294+
!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
13301295
LL_ADC_EnableInternalRegulator(adc);
13311296
k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
13321297
#endif
@@ -1362,16 +1327,13 @@ static int adc_stm32_init(const struct device *dev)
13621327
LL_ADC_CLOCK_ASYNC_DIV4);
13631328
#endif
13641329

1365-
#if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
1366-
!defined(CONFIG_SOC_SERIES_STM32F4X) && \
1367-
!defined(CONFIG_SOC_SERIES_STM32F7X) && \
1368-
!defined(CONFIG_SOC_SERIES_STM32L1X)
1330+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
13691331

1370-
#if !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5)
1332+
#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
13711333
adc_stm32_disable(adc);
13721334
adc_stm32_calib(dev);
13731335
adc_stm32_calib_delay(dev);
1374-
#endif /* !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5) */
1336+
#endif /* !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
13751337
#endif
13761338

13771339
err = adc_stm32_enable(adc);
@@ -1381,11 +1343,11 @@ static int adc_stm32_init(const struct device *dev)
13811343

13821344
config->irq_cfg_func();
13831345

1384-
#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(STM32F3X_ADC_V2_5)
1346+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
13851347
adc_stm32_calib_delay(dev);
13861348
adc_stm32_calib(dev);
13871349
LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
1388-
#endif /* !defined(CONFIG_SOC_SERIES_STM32F1X) && !defined(STM32F3X_ADC_V2_5) */
1350+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
13891351

13901352
#ifdef CONFIG_SOC_SERIES_STM32H7X
13911353
/*

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