boards: x86: acrn : Add configurations for acrn_ehl_crb

aasthagr · nashif · commit b64443272033 · 2021-01-11T16:11:59.000-05:00
Adding acrn configurations specific to the platform
on which acrn boots zephyr, Only the EHL specifc
configurations for now. Keeping the HW clock frequency to
1900Mhz for EHL and using the new APIc timer driver.

Signed-off-by: Aastha Grover &lt;aastha.grover@intel.com&gt;
diff --git a/boards/x86/acrn/acrn_ehl_crb.dts b/boards/x86/acrn/acrn_ehl_crb.dts
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "acrn.dts"
diff --git a/boards/x86/acrn/acrn_ehl_crb.yaml b/boards/x86/acrn/acrn_ehl_crb.yaml
@@ -0,0 +1,7 @@
+identifier: acrn_ehl_crb
+name: ACRN on EHL configuration
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 8192
diff --git a/boards/x86/acrn/acrn_ehl_crb_defconfig b/boards/x86/acrn/acrn_ehl_crb_defconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_IA32=y
+CONFIG_BOARD_ACRN=y
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_APIC_TIMER=y
+CONFIG_X2APIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1900000000
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n
+CONFIG_X86_MMU_PAGE_POOL_PAGES=29
diff --git a/tests/benchmarks/boot_time/testcase.yaml b/tests/benchmarks/boot_time/testcase.yaml
@@ -2,6 +2,6 @@ tests:
   benchmark.kernel.boot_time:
     arch_allow: x86 arm posix
     platform_exclude: qemu_x86 qemu_x86_coverage qemu_x86_64 qemu_x86_nommu
-      minnowboard acrn
+      minnowboard acrn acrn_ehl_crb
     tags: benchmark
     filter: CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 1000000
