drivers: ethernet: eth_stm32_hal: Add stm32n6 ethernet support

-Update the ETH_STM32_HAL menu configuration to conditionally
 select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X is enabled.

-Align Ethernet descriptors to 32 bytes for STM32N6 to ensure
 efficient DMA operations and improve cache line efficiency
 and overall performance

-Add RISAF configuration in eth_initialize function for STM32N6
 series to set up master and slave security attributes
 for the Ethernet peripheral.

-Ensure RISAF configuration is done before enabling
 the Ethernet clock to maintain proper security attributes.

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <[email protected]>

Author: marwaiehm-st

drivers/ethernet/Kconfig.stm32_hal

@@ -9,11 +9,12 @@ menuconfig ETH_STM32_HAL
 	default y
 	depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
 	select USE_STM32_HAL_ETH
-	select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
+	select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X
+	select NOCACHE_MEMORY if (SOC_SERIES_STM32H7X && CPU_CORTEX_M7) || SOC_SERIES_STM32N6X
 	select HWINFO
 	select ETH_DSA_SUPPORT
 	select PINCTRL
-	select MDIO if SOC_SERIES_STM32H5X || SOC_SERIES_STM32H7X
+	select MDIO if DT_HAS_ST_STM32_MDIO_ENABLED
 	imply CRC
 	help
 	  Enable STM32 HAL based Ethernet driver. It is available for
@@ -26,7 +27,8 @@ choice ETH_STM32_HAL_API_VERSION
 
 config ETH_STM32_HAL_API_V2
 	bool "Use official STM32Cube HAL driver"
-	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
+	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X
+	select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X
 	help
 	  Use the official STM32Cube HAL driver instead of the legacy one.
 

drivers/ethernet/eth_stm32_hal.c

@@ -131,8 +131,16 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
 #define __eth_stm32_buf  __aligned(4)
 #endif
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+static ETH_DMADescTypeDef
+	dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
+static ETH_DMADescTypeDef
+	dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
+#else
 static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
 static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
+#endif
+
 static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf;
 static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf;
 
@@ -842,7 +850,12 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 		CONTAINER_OF(heth, struct eth_stm32_hal_dev_data, heth);
 
 	switch (error_code) {
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	case HAL_ETH_ERROR_DMA_CH0:
+	case HAL_ETH_ERROR_DMA_CH1:
+#else
 	case HAL_ETH_ERROR_DMA:
+#endif
 		dma_error = HAL_ETH_GetDMAError(heth);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
@@ -939,6 +952,32 @@ static void generate_mac(uint8_t *mac_addr)
 #endif
 }
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+/**
+ * Configures the RISAF (RIF Security Attribute Framework) for Ethernet on STM32N6.
+ * This function sets up the master and slave security attributes for the Ethernet peripheral.
+ */
+
+static void RISAF_Config(void)
+{
+	/* Define and initialize the master configuration structure */
+	RIMC_MasterConfig_t RIMC_master = {0};
+
+	/* Enable the clock for the RIFSC (RIF Security Controller) */
+	__HAL_RCC_RIFSC_CLK_ENABLE();
+
+	RIMC_master.MasterCID = RIF_CID_1;
+	RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
+
+	/* Configure the master attributes for the Ethernet peripheral (ETH1) */
+	HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_ETH1, &RIMC_master);
+
+	/* Set the secure and privileged attributes for the Ethernet peripheral (ETH1) as a slave */
+	HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_ETH1,
+					      RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
+}
+#endif
+
 static int eth_initialize(const struct device *dev)
 {
 	struct eth_stm32_hal_dev_data *dev_data;
@@ -961,6 +1000,11 @@ static int eth_initialize(const struct device *dev)
 		return -ENODEV;
 	}
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	/* RISAF Configuration */
+	RISAF_Config();
+#endif
+
 	/* enable clock */
 	ret = clock_control_on(dev_data->clock,
 		(clock_control_subsys_t)&cfg->pclken);
@@ -1193,8 +1237,15 @@ static int eth_init_api_v2(const struct device *dev)
 	dev_data = dev->data;
 	heth = &dev_data->heth;
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
+		heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
+		heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
+	}
+#else
 	heth->Init.TxDesc = dma_tx_desc_tab;
 	heth->Init.RxDesc = dma_rx_desc_tab;
+#endif
 	heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
 
 	hal_ret = HAL_ETH_Init(heth);