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doc: bsim boards: Typo fixes
Just a few grammar fixes Signed-off-by: Alberto Escolar Piedras <[email protected]>
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boards/native/doc/bsim_boards_design.rst

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typically x86. x86 is little endian, which is typically also the case for the
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target architecture. If this is not the case, embedded code which works in one
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may not work in the other due to endianness bugs.
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Note that Zephyr code is be written to support both big and little endian.
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Note that Zephyr's code should be written to support both big and little endian.
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- WordSize: The bsim targets, as well as normal embedded targets are 32 bit
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targets. In the case of the bsim targets this is done by explicitly targeting
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x86 (ILP32 ABI) instead of x86_64. This is done purposefully to provide more

boards/native/nrf_bsim/doc/nrf52_bsim.rst

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Overview
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********
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To allow simulating a nRF52833 SOC a Zephyr target boards is provided: the
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To allow simulating a nRF52833 SOC, a Zephyr target board is provided: the
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nrf52_bsim.
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This uses `BabbleSim`_ to simulate the radio activity, and the

boards/native/nrf_bsim/doc/nrf54l15bsim.rst

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.. _nrf54l15bsim:
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NRF54L15 simulated boards (BabbleSim)
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#####################################
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NRF54L15 simulated board (BabbleSim)
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####################################
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.. contents::
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:depth: 1
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Overview
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********
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To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
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To allow simulating nRF54L15 SOCs, a Zephyr target board is provided: the
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``nrf54l15bsim/nrf54l15/cpuapp``.
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This uses `BabbleSim`_ to simulate the radio activity, and the
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This simulated target does **not** yet support targeting the cpuflpr core.
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This boards include models of some of the nRF54L15 SOC peripherals:
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This board includes models of some of the nRF54L15 SOC peripherals:
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* AAR (Accelerated Address Resolver)
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* CCM (AES CCM mode encryption)

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