drivers: can: m_can variant for STM32H7

* New m_can driver variant for STM32H7, as it uses the complete m_can
register set.
* Fix definitions for CAN_MCAN_RXF0S_F0FL, CAN_MCAN_TXEFC_EFSA_POS.

Signed-off-by: Jeremy Wood <[email protected]>

Author: JeremyBCD

drivers/can/CMakeLists.txt

@@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN can_mcux_flexcan.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_SAM          can_sam.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_STM32        can_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_STM32FD      can_stm32fd.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_STM32H7      can_stm32h7.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_RCAR         can_rcar.c)
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE        can_handlers.c)

drivers/can/Kconfig

@@ -96,6 +96,7 @@ config CAN_AUTO_BUS_OFF_RECOVERY
 source "drivers/can/Kconfig.sam"
 source "drivers/can/Kconfig.stm32"
 source "drivers/can/Kconfig.stm32fd"
+source "drivers/can/Kconfig.stm32h7"
 source "drivers/can/Kconfig.mcux"
 source "drivers/can/Kconfig.mcp2515"
 source "drivers/can/Kconfig.mcan"

drivers/can/Kconfig.mcan

@@ -10,7 +10,8 @@ config CAN_MCAN
 	help
 	  Enable Bosch m_can driver.
 	  This driver supports the Bosch m_can IP. This IP is built into the
-	  STM32G4, STM32G0 and the Microchip SAM controllers with CAN-FD.
+	  STM32G4, STM32G0, STM32H7, and the Microchip SAM controllers with
+	  CAN-FD.
 
 if CAN_MCAN
 

drivers/can/Kconfig.stm32h7

@@ -0,0 +1,32 @@
+# STM32H7 FD-CAN configuration options
+
+# Copyright (c) 2022 Blue Clover
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_STM32_H7 := st,stm32h7-fdcan
+
+config CAN_STM32H7
+	bool "STM32H7 FDCAN driver"
+	default $(dt_compat_enabled,$(DT_COMPAT_STM32_H7))
+	select CAN_MCAN
+	select USE_STM32_LL_RCC
+
+if CAN_STM32H7
+
+config CAN_MAX_STD_ID_FILTER
+	int "Maximum number of std ID filters"
+	default 28
+	range 0 28
+	help
+	  Defines the maximum number of filters with standard ID (11-bit)
+	  that can be attached.
+
+config CAN_MAX_EXT_ID_FILTER
+	int "Maximum number of ext ID filters"
+	default 8
+	range 0 8
+	help
+	  Defines the maximum number of filters with extended ID (29-bit)
+	  that can be attached.
+
+endif #CAN_STM32H7

drivers/can/can_mcan.c

@@ -297,10 +297,14 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
 		(can->crel & CAN_MCAN_CREL_DAY) >> CAN_MCAN_CREL_DAY_POS);
 
 #ifndef CONFIG_CAN_STM32FD
+	uint32_t mrba = 0;
+#ifdef CONFIG_CAN_STM32H7
+	mrba = (uint32_t)msg_ram;
+#endif
 #ifdef CONFIG_CAN_MCUX_MCAN
-	uint32_t mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;
-
+	mrba = (uint32_t)msg_ram & CAN_MCAN_MRBA_BA_MSK;
 	can->mrba = mrba;
+#endif
 	can->sidfc = (((uint32_t)msg_ram->std_filt - mrba) & CAN_MCAN_SIDFC_FLSSA_MSK) |
 		(ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
 	can->xidfc = (((uint32_t)msg_ram->ext_filt - mrba) & CAN_MCAN_XIDFC_FLESA_MSK) |
@@ -312,24 +316,8 @@ int can_mcan_init(const struct device *dev, const struct can_mcan_config *cfg,
 	can->rxbc = (((uint32_t)msg_ram->rx_buffer - mrba) & CAN_MCAN_RXBC_RBSA);
 	can->txefc = (((uint32_t)msg_ram->tx_event_fifo - mrba) & CAN_MCAN_TXEFC_EFSA_MSK) |
 		(ARRAY_SIZE(msg_ram->tx_event_fifo) << CAN_MCAN_TXEFC_EFS_POS);
-	can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA_MSK) |
-		    (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
-#else /* CONFIG_CAN_MCUX_MCAN */
-	can->sidfc = ((uint32_t)msg_ram->std_filt & CAN_MCAN_SIDFC_FLSSA_MSK) |
-		     (ARRAY_SIZE(msg_ram->std_filt) << CAN_MCAN_SIDFC_LSS_POS);
-	can->xidfc = ((uint32_t)msg_ram->ext_filt & CAN_MCAN_XIDFC_FLESA_MSK) |
-		     (ARRAY_SIZE(msg_ram->ext_filt) << CAN_MCAN_XIDFC_LSS_POS);
-	can->rxf0c = ((uint32_t)msg_ram->rx_fifo0 & CAN_MCAN_RXF0C_F0SA) |
-		     (ARRAY_SIZE(msg_ram->rx_fifo0) << CAN_MCAN_RXF0C_F0S_POS);
-	can->rxf1c = ((uint32_t)msg_ram->rx_fifo1 & CAN_MCAN_RXF1C_F1SA) |
-		     (ARRAY_SIZE(msg_ram->rx_fifo1) << CAN_MCAN_RXF1C_F1S_POS);
-	can->rxbc = ((uint32_t)msg_ram->rx_buffer & CAN_MCAN_RXBC_RBSA);
-	can->txefc = ((uint32_t)msg_ram->tx_event_fifo & CAN_MCAN_TXEFC_EFSA_MSK) |
-		     (ARRAY_SIZE(msg_ram->tx_event_fifo) <<
-		     CAN_MCAN_TXEFC_EFS_POS);
-	can->txbc = ((uint32_t)msg_ram->tx_buffer & CAN_MCAN_TXBC_TBSA) |
-		    (ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
-#endif /* !CONFIG_CAN_MCUX_MCAN */
+	can->txbc = (((uint32_t)msg_ram->tx_buffer - mrba) & CAN_MCAN_TXBC_TBSA) |
+		(ARRAY_SIZE(msg_ram->tx_buffer) << CAN_MCAN_TXBC_TFQS_POS);
 
 	if (sizeof(msg_ram->tx_buffer[0].data) <= 24) {
 		can->txesc = (sizeof(msg_ram->tx_buffer[0].data) - 8) / 4;

drivers/can/can_mcan_int.h

@@ -1084,7 +1084,7 @@
 
 /* Rx FIFO 0 Fill Level */
 #define CAN_MCAN_RXF0S_F0FL_POS      (0U)
-#define CAN_MCAN_RXF0S_F0FL_MSK      (0x3FUL << CAN_MCAN_RXF0S_F0FL_POS)
+#define CAN_MCAN_RXF0S_F0FL_MSK      (0x7FUL << CAN_MCAN_RXF0S_F0FL_POS)
 #define CAN_MCAN_RXF0S_F0FL          CAN_MCAN_RXF0S_F0FL_MSK
 /* Rx FIFO 0 Get Index */
 #define CAN_MCAN_RXF0S_F0GI_POS      (8U)