dts: nordic: nrf54: add nRF54L20 FLPR core

Added support for nRF54L20 FLPR core in devicetree.

Signed-off-by: Michał Stasiak <[email protected]>

Author: mstasiaknordic

dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi

@@ -10,6 +10,11 @@ cpu: &cpuapp {};
 systick: &cpuapp_systick {};
 nvic: &cpuapp_nvic {};
 
+/delete-node/ &cpuflpr;
+/delete-node/ &cpuflpr_rram;
+/delete-node/ &cpuflpr_sram;
+/delete-node/ &cpuflpr_clic;
+
 / {
 	soc {
 		compatible = "simple-bus";
@@ -23,6 +28,27 @@ nvic: &cpuapp_nvic {};
 	};
 };
 
+&cpuflpr_vpr {
+	cpuapp_vevif_rx: mailbox@1 {
+		compatible = "nordic,nrf-vevif-event-rx";
+		reg = <0x0 0x1000>;
+		status = "disabled";
+		interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
+		#mbox-cells = <1>;
+		nordic,events = <1>;
+		nordic,events-mask = <0x00100000>;
+	};
+
+	cpuapp_vevif_tx: mailbox@0 {
+		compatible = "nordic,nrf-vevif-task-tx";
+		reg = <0x0 0x1000>;
+		#mbox-cells = <1>;
+		nordic,tasks = <7>;
+		nordic,tasks-mask = <0x007f0000>;
+		status = "disabled";
+	};
+};
+
 &cpuapp_ppb {
 	compatible = "simple-bus";
 	ranges;

dts/common/nordic/nrf54l20.dtsi

@@ -11,6 +11,10 @@
 
 /delete-node/ &sw_pwm;
 
+/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
+#define NRF_DOMAIN_ID_APPLICATION 0
+#define NRF_DOMAIN_ID_FLPR 1
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -33,6 +37,14 @@
 				swo-ref-frequency = <DT_FREQ_M(128)>;
 			};
 		};
+
+		cpuflpr: cpu@1 {
+			compatible = "nordic,vpr";
+			reg = <1>;
+			device_type = "cpu";
+			riscv,isa = "rv32emc";
+			nordic,bus-width = <64>;
+		};
 	};
 
 	clocks {
@@ -78,10 +90,18 @@
 
 		cpuapp_sram: memory@20000000 {
 			compatible = "mmio-sram";
-			reg = <0x20000000 DT_SIZE_K(511)>;
+			reg = <0x20000000 DT_SIZE_K(447)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20000000 0x6fc00>;
+		};
+
+		cpuflpr_sram: memory@2006fc00 {
+			compatible = "mmio-sram";
+			reg = <0x2006fc00 DT_SIZE_K(64)>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			ranges = <0x0 0x20000000 0x7fc00>;
+			ranges = <0x0 0x2006fc00 0x10000>;
 		};
 
 		global_peripherals: peripheral@50000000 {
@@ -107,6 +127,24 @@
 				status = "disabled";
 			};
 
+			cpuflpr_vpr: vpr@4c000 {
+				compatible = "nordic,nrf-vpr-coprocessor";
+				reg = <0x4c000 0x1000>;
+				ranges = <0x0 0x4c000 0x1000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				status = "disabled";
+
+				cpuflpr_clic: interrupt-controller@f0000000 {
+					compatible = "nordic,nrf-clic";
+					reg = <0xf0000000 0x143c>;
+					interrupt-controller;
+					#interrupt-cells = <2>;
+					#address-cells = <1>;
+					status = "disabled";
+				};
+			};
+
 			spi00: spi@4d000 {
 				/*
 				 * This spi node can be either SPIM or SPIS,
@@ -737,7 +775,14 @@
 
 			cpuapp_rram: rram@0 {
 				compatible = "soc-nv-flash";
-				reg = <0x0 DT_SIZE_K(2028)>;
+				reg = <0x0 DT_SIZE_K(1972)>;
+				erase-block-size = <4096>;
+				write-block-size = <16>;
+			};
+
+			cpuflpr_rram: rram@1ed000 {
+				compatible = "soc-nv-flash";
+				reg = <0x1ed000 DT_SIZE_K(64)>;
 				erase-block-size = <4096>;
 				write-block-size = <16>;
 			};

dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf54l20.dtsi>
+
+cpu: &cpuflpr {};
+clic: &cpuflpr_clic {};
+
+/delete-node/ &cpuapp;
+/delete-node/ &cpuapp_rram;
+/delete-node/ &cpuapp_ppb;
+/delete-node/ &cpuapp_sram;
+
+/ {
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&cpuflpr_clic>;
+		ranges;
+	};
+};
+
+&cpuflpr {
+	cpuflpr_vevif_rx: mailbox {
+		compatible = "nordic,nrf-vevif-task-rx";
+		status = "disabled";
+		interrupt-parent = <&cpuflpr_clic>;
+		interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <17 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <18 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <19 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <20 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <21 NRF_DEFAULT_IRQ_PRIORITY>,
+			     <22 NRF_DEFAULT_IRQ_PRIORITY>;
+		#mbox-cells = <1>;
+		nordic,tasks = <7>;
+		nordic,tasks-mask = <0x007f0000>;
+	};
+};
+
+&cpuflpr_vpr {
+	cpuflpr_vevif_tx: mailbox {
+		compatible = "nordic,nrf-vevif-event-tx";
+		#mbox-cells = <1>;
+		nordic,events = <1>;
+		nordic,events-mask = <0x00100000>;
+		status = "disabled";
+	};
+};
+
+&cpuflpr_clic {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&gpiote20 {
+	interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
+};
+
+&gpiote30 {
+	interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
+};