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adsp: ace: Non-maskable interrupt handling
The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers so its occurrence cannot be confirmed. Removed the code that checked if the interrupt flag is set. Signed-off-by: Adrian Warecki <[email protected]>
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soc/xtensa/intel_adsp/ace/_soc_inthandlers.h

Lines changed: 5 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -117,17 +117,12 @@ static inline int _xtensa_handle_one_int3(unsigned int mask)
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static inline int _xtensa_handle_one_int5(unsigned int mask)
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{
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int irq;
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if (mask & BIT(8)) {
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mask = BIT(8);
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irq = 8;
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goto handle_irq;
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}
120+
/* It is a Non-maskable interrupt handler.
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* The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers
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* so mask parameter is always 0.
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*/
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_sw_isr_table[8].isr(_sw_isr_table[8].arg);
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return 0;
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handle_irq:
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_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
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return mask;
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}
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static inline int _xtensa_handle_one_int0(unsigned int mask)

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