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tests/drivers/clock_control: stm32: Add stm32_common_devices tests
Add a test section to enable device clock source selection testing. Test targets I2C1 device which supports clock source selection on all SOCs using this driver except L1 Initial test done on wb target. Signed-off-by: Erwan Gouriou <[email protected]>
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‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(stm32_clock_configuration_common_devices)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})

‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f0_i2c1_hsi.overlay‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ hse-bypass;
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/delete-property/ clock-frequency;
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};
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&clk_hsi {
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status = "disabled";
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};
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&clk_lse {
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status = "disabled";
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};
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&clk_lsi {
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status = "disabled";
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};
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&pll {
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/delete-property/ mul;
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/delete-property/ div;
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/delete-property/ prediv;
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/delete-property/ xtpre;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_hsi {
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clock-frequency = <DT_FREQ_M(8)>;
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status = "okay";
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};
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&pll {
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prediv = <2>;
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mul = <8>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(32)>;
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};
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&i2c1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f3_i2c1_hsi.overlay‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ hse-bypass;
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/delete-property/ clock-frequency;
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};
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&clk_hsi {
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status = "disabled";
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};
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&clk_lse {
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status = "disabled";
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};
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&clk_lsi {
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status = "disabled";
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};
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&pll {
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/delete-property/ mul;
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/delete-property/ div;
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/delete-property/ prediv;
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/delete-property/ xtpre;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_hsi {
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clock-frequency = <DT_FREQ_M(8)>;
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status = "okay";
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};
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&pll {
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prediv = <2>;
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mul = <8>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(32)>;
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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};
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&i2c1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_hsi_lptim1_lse.overlay‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ hse-bypass;
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/delete-property/ clock-frequency;
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};
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&clk_hsi {
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status = "disabled";
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};
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&pll {
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-p;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_hsi {
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status = "okay";
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};
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&clk_lse {
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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};
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&i2c1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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status = "okay";
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};
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&lptim1 {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
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<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g0_i2c1_sysclk_lptim1_lsi.overlay‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ hse-bypass;
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/delete-property/ clock-frequency;
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};
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&clk_hsi {
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status = "disabled";
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};
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&pll {
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-p;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_hsi {
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status = "okay";
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};
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&clk_lsi {
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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};
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&i2c1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
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<&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
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status = "okay";
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};
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&lptim1 {
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
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<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
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status = "okay";
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};

‎tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/g4_i2c1_hsi.overlay‎

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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Clocks clean up config
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* Aim is to avoid conflict with specific default board configuration
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*/
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&clk_hse {
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status = "disabled";
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/delete-property/ hse-bypass;
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/delete-property/ clock-frequency;
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};
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&clk_hsi {
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status = "disabled";
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};
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&pll {
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/delete-property/ div-m;
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/delete-property/ mul-n;
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/delete-property/ div-p;
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/delete-property/ div-q;
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/delete-property/ div-r;
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/delete-property/ clocks;
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status = "disabled";
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};
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&rcc {
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/delete-property/ clocks;
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/delete-property/ clock-frequency;
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};
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/* Core set up
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* Aim of this part is to provide a base working clock config
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*/
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&clk_hsi {
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status = "okay";
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};
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&pll {
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div-m = <1>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(64)>;
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ahb-prescaler = <1>;
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apb1-prescaler = <2>;
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};
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&i2c1 {
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/delete-property/ clocks;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
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<&rcc STM32_SRC_HSI I2C1_SEL(2)>;
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status = "okay";
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};

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