xtensa: mmu: allocate scratch registers for MMU

When MMU is enabled, we need some scratch registers to preload
page table entries. So update gen_zsr.py to that.

Signed-off-by: Daniel Leung <[email protected]>
Signed-off-by: Flavio Ceolin <[email protected]>

Author: dcpleung

arch/xtensa/core/CMakeLists.txt

@@ -59,6 +59,7 @@ add_custom_command(OUTPUT ${CORE_ISA_DM}
 set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zsr.h)
 add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
   COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
+                               $<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
                                ${CORE_ISA_DM} ${ZSR_H})
 add_custom_target(zsr_h DEPENDS ${ZSR_H})
 add_dependencies(zephyr_interface zsr_h)

arch/xtensa/core/gen_zsr.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # Copyright (c) 2022 Intel corporation
 # SPDX-License-Identifier: Apache-2.0
-import sys
+import argparse
 import re
 
 # Scratch register allocator.  Zephyr uses multiple Xtensa SRs as
@@ -11,10 +11,26 @@
 # -dM") core-isa.h file for the current architecture and assigns
 # registers to usages.
 
-NEEDED = ("A0SAVE", "CPU", "FLUSH")
+def parse_args():
+    parser = argparse.ArgumentParser(allow_abbrev=False)
 
-coreisa = sys.argv[1]
-outfile = sys.argv[2]
+    parser.add_argument("--mmu", action="store_true",
+                        help="Enable scratch registers for MMU usage")
+    parser.add_argument("coreisa",
+                        help="Path to preprocessed core-isa.h")
+    parser.add_argument("outfile",
+                        help="Output file")
+
+    return parser.parse_args()
+
+args = parse_args()
+
+NEEDED = ["A0SAVE", "CPU", "FLUSH"]
+if args.mmu:
+    NEEDED += ["MMU_0", "MMU_1", "DBLEXC"]
+
+coreisa = args.coreisa
+outfile = args.outfile
 
 syms = {}
 

arch/xtensa/core/xtensa-asm2-util.S

@@ -439,14 +439,14 @@ _handle_tlb_miss_kernel:
 .global _DoubleExceptionVector
 _DoubleExceptionVector:
 #ifdef CONFIG_XTENSA_MMU
-	wsr a0, ZSR_A0SAVE
+	wsr a0, ZSR_DBLEXC
 	rsync
 
 	rsr.exccause a0
 	addi a0, a0, -EXCCAUSE_DTLB_MISS
 	beqz a0, _handle_tlb_miss_dblexc
 
-	rsr a0, ZSR_A0SAVE
+	rsr a0, ZSR_DBLEXC
 
 	j _Level1Vector
 #else
@@ -482,7 +482,7 @@ _handle_tlb_miss_dblexc:
 	rsr.ptevaddr a0
 	l32i a0, a0, 0
 
-	rsr a0, ZSR_A0SAVE
+	rsr a0, ZSR_DBLEXC
 	rfde
 #endif
 .popsection

arch/xtensa/include/xtensa-asm2-s.h

@@ -558,8 +558,8 @@ _Level\LVL\()VectorHelper :
 _Level\LVL\()Vector:
 #endif
 #ifdef CONFIG_XTENSA_MMU
-	wsr.ZSR_EXTRA0 a2
-	wsr.ZSR_EXTRA1 a3
+	wsr.ZSR_MMU_0 a2
+	wsr.ZSR_MMU_1 a3
 	rsync
 
 	/* Calculations below will clobber registers used.
@@ -579,8 +579,8 @@ _Level\LVL\()Vector:
 	rsr.ZSR_CPU a3
 	PRELOAD_PTEVADDR a3, a2
 
-	rsr.ZSR_EXTRA1 a3
-	rsr.ZSR_EXTRA0 a2
+	rsr.ZSR_MMU_1 a3
+	rsr.ZSR_MMU_0 a2
 #endif /* CONFIG_XTENSA_MMU */
 	addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
 	s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET