|
| 1 | +/* |
| 2 | + * Copyright 2023 Google LLC |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +/dts-v1/; |
| 8 | +#include <st/h7/stm32h747Xi_m7.dtsi> |
| 9 | +#include <st/h7/stm32h747xihx-pinctrl.dtsi> |
| 10 | +#include "arduino_giga_r1.dtsi" |
| 11 | + |
| 12 | +/ { |
| 13 | + model = "Arduino GIGA R1 WiFi Board (M7)"; |
| 14 | + compatible = "arduino,giga-r1"; |
| 15 | + |
| 16 | + chosen { |
| 17 | + zephyr,console = &usart1; |
| 18 | + zephyr,shell-uart = &usart1; |
| 19 | + zephyr,uart-mcumgr = &usart1; |
| 20 | + zephyr,sram = &sram0; |
| 21 | + zephyr,flash = &flash0; |
| 22 | + zephyr,canbus = &can2; |
| 23 | + zephyr,code-partition = &slot0_partition; |
| 24 | + }; |
| 25 | + |
| 26 | + sdram1: sdram@c0000000 { |
| 27 | + compatible = "zephyr,memory-region", "mmio-sram"; |
| 28 | + device_type = "memory"; |
| 29 | + reg = <0xc0000000 DT_SIZE_M(8)>; |
| 30 | + zephyr,memory-region = "SDRAM1"; |
| 31 | + zephyr,memory-region-mpu = "RAM"; |
| 32 | + }; |
| 33 | + |
| 34 | + aliases { |
| 35 | + led0 = &red_led; |
| 36 | + led1 = &green_led; |
| 37 | + sw0 = &user_button; |
| 38 | + spi-flash0 = &n25q128a1; |
| 39 | + }; |
| 40 | +}; |
| 41 | + |
| 42 | +&clk_hse { |
| 43 | + status = "okay"; |
| 44 | + clock-frequency = <DT_FREQ_M(16)>; |
| 45 | +}; |
| 46 | + |
| 47 | +&clk_lse { |
| 48 | + status = "okay"; |
| 49 | +}; |
| 50 | + |
| 51 | +&clk_hsi48 { |
| 52 | + status = "okay"; |
| 53 | +}; |
| 54 | + |
| 55 | +&pll { |
| 56 | + div-m = <2>; |
| 57 | + mul-n = <120>; |
| 58 | + div-p = <2>; |
| 59 | + div-q = <4>; |
| 60 | + div-r = <2>; |
| 61 | + clocks = <&clk_hse>; |
| 62 | + status = "okay"; |
| 63 | +}; |
| 64 | + |
| 65 | +&rcc { |
| 66 | + clocks = <&pll>; |
| 67 | + clock-frequency = <DT_FREQ_M(480)>; |
| 68 | +}; |
| 69 | + |
| 70 | +&usart1 { |
| 71 | + status = "okay"; |
| 72 | + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pb7>; |
| 73 | + pinctrl-names = "default"; |
| 74 | + current-speed = <115200>; |
| 75 | +}; |
| 76 | + |
| 77 | +&usart6 { |
| 78 | + status = "disabled"; |
| 79 | + pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pc7>; |
| 80 | + pinctrl-names = "default"; |
| 81 | + current-speed = <115200>; |
| 82 | +}; |
| 83 | + |
| 84 | +&uart4 { |
| 85 | + status = "disabled"; |
| 86 | + pinctrl-0 = <&uart4_tx_ph13 &uart4_rx_pi9>; |
| 87 | + pinctrl-names = "default"; |
| 88 | + current-speed = <115200>; |
| 89 | +}; |
| 90 | + |
| 91 | +&uart7 { |
| 92 | + status = "disabled"; |
| 93 | + pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pa8 |
| 94 | + &uart7_cts_pf9 &uart7_rts_pf8>; |
| 95 | + pinctrl-names = "default"; |
| 96 | + current-speed = <115200>; |
| 97 | + status = "okay"; |
| 98 | + hw-flow-control; |
| 99 | +}; |
| 100 | + |
| 101 | +&i2c4 { |
| 102 | + status = "okay"; |
| 103 | + pinctrl-0 = <&i2c4_scl_pb6 &i2c4_sda_ph12>; |
| 104 | + pinctrl-names = "default"; |
| 105 | + clock-frequency = <I2C_BITRATE_STANDARD>; |
| 106 | +}; |
| 107 | + |
| 108 | +&i2c1 { |
| 109 | + status = "disabled"; |
| 110 | + pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; |
| 111 | + pinctrl-names = "default"; |
| 112 | + clock-frequency = <I2C_BITRATE_FAST>; |
| 113 | +}; |
| 114 | + |
| 115 | +&i2c2 { |
| 116 | + status = "disabled"; |
| 117 | + pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_pb11>; |
| 118 | + pinctrl-names = "default"; |
| 119 | + clock-frequency = <I2C_BITRATE_FAST>; |
| 120 | +}; |
| 121 | + |
| 122 | +&spi5 { |
| 123 | + status = "okay"; |
| 124 | + pinctrl-0 = <&spi5_nss_pk1 &spi5_sck_ph6 |
| 125 | + &spi5_miso_pj11 &spi5_mosi_pj10>; |
| 126 | + pinctrl-names = "default"; |
| 127 | +}; |
| 128 | + |
| 129 | +&can2 { |
| 130 | + status = "okay"; |
| 131 | + pinctrl-0 = <&fdcan2_tx_pb13 &fdcan2_rx_pb5>; |
| 132 | + pinctrl-names = "default"; |
| 133 | + bus-speed = <125000>; |
| 134 | + bus-speed-data = <1000000>; |
| 135 | +}; |
| 136 | + |
| 137 | +&flash0 { |
| 138 | + partitions { |
| 139 | + compatible = "fixed-partitions"; |
| 140 | + #address-cells = <1>; |
| 141 | + #size-cells = <1>; |
| 142 | + |
| 143 | + boot_partition: partition@0 { |
| 144 | + label = "bootloader"; |
| 145 | + reg = <0x0 0x40000>; |
| 146 | + read-only; |
| 147 | + }; |
| 148 | + |
| 149 | + slot0_partition: partition@40000 { |
| 150 | + label = "image-0"; |
| 151 | + reg = <0x40000 0x000c0000>; |
| 152 | + }; |
| 153 | + }; |
| 154 | +}; |
| 155 | + |
| 156 | +&quadspi { |
| 157 | + pinctrl-0 = <&quadspi_clk_pf10 &quadspi_bk1_ncs_pg6 |
| 158 | + &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12 |
| 159 | + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pf6>; |
| 160 | + pinctrl-names = "default"; |
| 161 | + status = "okay"; |
| 162 | + |
| 163 | + n25q128a1: qspi-nor-flash@0 { |
| 164 | + compatible = "st,stm32-qspi-nor"; |
| 165 | + reg = <0>; |
| 166 | + qspi-max-frequency = <72000000>; |
| 167 | + size = <DT_SIZE_M(16*8)>; |
| 168 | + status = "okay"; |
| 169 | + |
| 170 | + partitions { |
| 171 | + compatible = "fixed-partitions"; |
| 172 | + #address-cells = <1>; |
| 173 | + #size-cells = <1>; |
| 174 | + |
| 175 | + slot1_partition: partition@0 { |
| 176 | + label = "image-1"; |
| 177 | + reg = <0x00000000 DT_SIZE_M(1)>; |
| 178 | + }; |
| 179 | + |
| 180 | + storage_partition: partition@100000 { |
| 181 | + label = "storage"; |
| 182 | + reg = <0x00100000 DT_SIZE_M(15)>; |
| 183 | + }; |
| 184 | + }; |
| 185 | + }; |
| 186 | +}; |
| 187 | + |
| 188 | +&rng { |
| 189 | + status = "okay"; |
| 190 | +}; |
| 191 | + |
| 192 | +&dac1 { |
| 193 | + status = "okay"; |
| 194 | + pinctrl-0 = <&dac1_out1_pa4 &dac1_out2_pa5>; |
| 195 | + pinctrl-names = "default"; |
| 196 | +}; |
| 197 | + |
| 198 | +&fmc { |
| 199 | + status = "okay"; |
| 200 | + pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 |
| 201 | + &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_ph2 |
| 202 | + &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15 |
| 203 | + |
| 204 | + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 |
| 205 | + &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 |
| 206 | + &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 |
| 207 | + &fmc_a14_pg4 &fmc_a15_pg5 |
| 208 | + |
| 209 | + &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 |
| 210 | + &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 |
| 211 | + &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 |
| 212 | + &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>; |
| 213 | + pinctrl-names = "default"; |
| 214 | + |
| 215 | + sdram { |
| 216 | + status = "okay"; |
| 217 | + |
| 218 | + power-up-delay = <100>; |
| 219 | + num-auto-refresh = <8>; |
| 220 | + mode-register = <0x220>; |
| 221 | + refresh-rate = <603>; |
| 222 | + |
| 223 | + bank@0 { |
| 224 | + reg = <0>; |
| 225 | + st,sdram-control = <STM32_FMC_SDRAM_NC_8 |
| 226 | + STM32_FMC_SDRAM_NR_12 |
| 227 | + STM32_FMC_SDRAM_MWID_16 |
| 228 | + STM32_FMC_SDRAM_NB_4 |
| 229 | + STM32_FMC_SDRAM_CAS_2 |
| 230 | + STM32_FMC_SDRAM_SDCLK_PERIOD_2 |
| 231 | + STM32_FMC_SDRAM_RBURST_ENABLE |
| 232 | + STM32_FMC_SDRAM_RPIPE_0>; |
| 233 | + st,sdram-timing = <2 6 4 6 2 2 2>; |
| 234 | + }; |
| 235 | + }; |
| 236 | +}; |
| 237 | + |
| 238 | +zephyr_udc0: &usbotg_fs { |
| 239 | + status = "okay"; |
| 240 | + pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; |
| 241 | + pinctrl-names = "default"; |
| 242 | +}; |
0 commit comments