dts: bindings: clock: add stm32n6 rcc clocks

Add STM32N6 RCC clock bindings

Signed-off-by: Guillaume Gautier <[email protected]>

Author: gautierg-st

dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml

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+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 CPU Clock
+  Describes the STM32N6 CPU clock multiplexer. On STM32N6, this is the CPU
+  clock that feeds the SysTick.
+  For instance:
+  &cpusw {
+    clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+    clock-frequency = <DT_FREQ_M(600)>;
+    status = "okay";
+  };
+
+compatible: "st,stm32n6-cpu-clock-mux"
+
+include:
+  - name: base.yaml
+    property-allowlist:
+      - status
+      - compatible
+      - clocks
+
+properties:
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for CPU clock (sysa_ck/sys_cpu_ck)

dts/bindings/clock/st,stm32n6-hse-clock.yaml

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+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32N6 HSE Clock
+
+compatible: "st,stm32n6-hse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+  hse-bypass:
+    type: boolean
+    description: |
+      HSE crystal oscillator bypass
+      Set to the property to by-pass the oscillator with an external clock.
+
+  hse-div2:
+    type: boolean
+    description: |
+      When set HSE output clock is divided by 2.
+      Otherwise, no prescaler is used.

dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml

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+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 Divider IC multiplexer
+  This node select a clock input and a divider.
+  For instance:
+    &ic6 {
+      pll-src = <2>;
+      div = <16>;
+      status = "okay";
+    };
+
+compatible: "st,stm32n6-ic-clock-mux"
+
+properties:
+  pll-src:
+    type: int
+    required: true
+    description: |
+        PLL clock source
+    enum:
+      - 1
+      - 2
+      - 3
+      - 4
+
+  ic-div:
+    type: int
+    description: |
+        ICx integer division factor
+        The input ICx frequency is divided by the specified value
+        Valid range: 1 - 256

dts/bindings/clock/st,stm32n6-pll-clock.yaml

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+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32N6 devices
+
+  It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
+
+  These PLLs can take one of clk_hse, clk_hsi or clk_msi as input clock, with
+  an input frequency from 5 to 50 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL has one output clock whose frequency can be computed with the
+  following formula:
+
+    f(PLL_P) = f(VCO clock) / (PLLP1 × PLLP2)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  Note: To reduce the power consumption, it is recommended to configure the VCOx
+        clock output to the lowest frequency.
+
+  The PLL output frequency must not exceed 3200 MHz.
+
+compatible: "st,stm32n6-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    required: true
+
+  div-m:
+    type: int
+    required: true
+    description: |
+        Prescaler for PLLx
+        input clock
+        Valid range: 1 - 63
+
+  mul-n:
+    type: int
+    required: true
+    description: |
+        PLLx multiplication factor for VCO
+        Valid range: 16 - 2500
+
+  div-p1:
+    type: int
+    description: |
+        PLLx DIVP1 division factor
+        Valid range: 1 - 7
+
+  div-p2:
+    type: int
+    description: |
+        PLLx DIVP2 division factor
+        Valid range: 1 - 7

dts/bindings/clock/st,stm32n6-rcc.yaml

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+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 Reset and Clock controller node for STM32N6 devices
+  This node is in charge of system clock ('SYSCLK') source selection and
+  System Clock Generation.
+
+  Configuring STM32 Reset and Clock controller node:
+
+  System clock source should be selected amongst the clock nodes available in "clocks"
+  node (typically 'clk_hse, clk_csi', 'pll', ...).
+  As part of this node configuration, SYSCLK frequency should also be defined, using
+  "clock-frequency" property.
+  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
+  prescaler properties.
+  Here is an example of correctly configured rcc node:
+  &rcc {
+    clocks = <&ic2>;
+    clock-frequency = <DT_FREQ_M(400)>;
+    ahb-prescaler = <2>;
+    apb1-prescaler = <1>;
+    apb2-prescaler = <1>;
+    apb4-prescaler = <1>;
+    apb5-prescaler = <1>;
+  }
+
+  Confere st,stm32-rcc binding for information about domain clocks configuration.
+
+compatible: "st,stm32n6-rcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 2
+
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for clock output
+
+  ahb-prescaler:
+    type: int
+    required: true
+    description: |
+        AHB clock prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+  apb1-prescaler:
+    type: int
+    required: true
+    description: |
+        CPU domain APB1 prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+  apb2-prescaler:
+    type: int
+    required: true
+    description: |
+        CPU domain APB2 prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+  apb4-prescaler:
+    type: int
+    required: true
+    description: |
+        CPU domain APB4 prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+  apb5-prescaler:
+    type: int
+    required: true
+    description: |
+        CPU domain APB5 prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+
+clock-cells:
+  - bus
+  - bits