riscv32: enable gen_isr_tables mechanism

Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <[email protected]>

Author: Andrew Boie

arch/common/Makefile.gen_isr_tables

@@ -2,14 +2,10 @@ GEN_ISR_TABLE := $(srctree)/arch/common/gen_isr_tables.py
 OUTPUT_SRC := isr_tables.c
 OUTPUT_OBJ := isr_tables.o
 
-ifeq ($(ARCH),arm)
-OUTPUT_FORMAT := elf32-littlearm
-OUTPUT_ARCH := arm
-else ifeq ($(ARCH),nios2)
-OUTPUT_FORMAT := elf32-littlenios2
-OUTPUT_ARCH := nios2
+ifeq ($(ARCH),riscv32)
+OUTPUT_FORMAT := elf32-littleriscv
 else
-$(error Output formats not defined for this architecture)
+OUTPUT_FORMAT := elf32-little$(ARCH)
 endif
 
 GEN_ISR_TABLE_EXTRA_ARGS :=

arch/riscv32/Kconfig

@@ -63,6 +63,13 @@ config RISCV_HAS_CPU_IDLE
 	default n
 	help
 	Does SOC has CPU IDLE instruction
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
 endmenu
 
 source "arch/riscv32/soc/*/Kconfig"

arch/riscv32/core/Makefile

@@ -1,5 +1,5 @@
 ccflags-y += -I$(srctree)/kernel/unified/include
 ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
 
-obj-y += isr.o reset.o sw_isr_table.o fatal.o irq_manage.o \
+obj-y += isr.o reset.o fatal.o irq_manage.o \
 	prep_c.o cpu_idle.o swap.o thread.o irq_offload.o

arch/riscv32/core/sw_isr_table.S

@@ -56,27 +56,14 @@ extern uint32_t __soc_get_irq(void);
 void _arch_irq_enable(unsigned int irq);
 void _arch_irq_disable(unsigned int irq);
 int _arch_irq_is_enabled(unsigned int irq);
+void _irq_spurious(void *unused);
 
 
 /**
  * Configure a static interrupt.
  *
  * All arguments must be computable by the compiler at build time.
  *
- * Internally this function does a few things:
- *
- * 1. The enum statement has no effect but forces the compiler to only
- * accept constant values for the irq_p parameter, very important as the
- * numerical IRQ line is used to create a named section.
- *
- * 2. An instance of struct _isr_table_entry is created containing the ISR and
- * its parameter. If you look at how _sw_isr_table is created, each entry in
- * the array is in its own section named by the IRQ line number. What we are
- * doing here is to override one of the default entries (which points to the
- * spurious IRQ handler) with what was supplied here.
- *
- * 3. interrupt priority is not supported by pulpino core
- *
  * @param irq_p IRQ line number
  * @param priority_p Interrupt priority
  * @param isr_p Interrupt service routine
@@ -87,11 +74,7 @@ int _arch_irq_is_enabled(unsigned int irq);
  */
 #define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
 ({ \
-	enum { IRQ = irq_p }; \
-	static struct _isr_table_entry _CONCAT(_isr_irq, irq_p) \
-		__attribute__ ((used)) \
-		__attribute__ ((section(STRINGIFY(_CONCAT(.gnu.linkonce.isr_irq, irq_p))))) = \
-			{isr_param_p, isr_p}; \
+	_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
 	irq_p; \
 })
 

include/arch/riscv32/arch.h

@@ -37,6 +37,8 @@ MEMORY
 {
     ROM (rx)  : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
     RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
+    /* Used by and documented in include/linker/intlist.ld */
+    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
 }
 
 SECTIONS
@@ -69,20 +71,11 @@ SECTIONS
     SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
 	{
 		. = ALIGN(4);
-
-		 KEEP(*(.isr_irq*))
-
-		 /* sections for IRQ0-9 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))
-
-		 /* sections for IRQ10-99 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
-
-		 /* sections for IRQ100-999 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
-
-		 KEEP(*(.openocd_debug))
-		 KEEP(*(".openocd_debug.*"))
+#ifdef CONFIG_GEN_SW_ISR_TABLE
+		KEEP(*(SW_ISR_TABLE))
+#endif
+		KEEP(*(.openocd_debug))
+		KEEP(*(".openocd_debug.*"))
 
 		_image_text_start = .;
 		*(.text)
@@ -160,5 +153,9 @@ SECTIONS
      _image_ram_end = .;
      _end = .; /* end of image */
 
+#ifdef CONFIG_GEN_ISR_TABLES
+#include <linker/intlist.ld>
+#endif
+
      GROUP_END(RAMABLE_REGION)
 }

include/arch/riscv32/common/linker.ld

@@ -33,6 +33,8 @@ MEMORY
     {
     INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE
     DATARAM  (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE
+    /* Used by and documented in include/linker/intlist.ld */
+    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
 }
 
 SECTIONS
@@ -80,9 +82,12 @@ SECTIONS
     SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
 	{
 		 . = ALIGN(4);
-		 *(.rodata)
-		 *(".rodata.*")
-		 *(.gnu.linkonce.r.*)
+#ifdef CONFIG_GEN_SW_ISR_TABLE
+		KEEP(*(SW_ISR_TABLE))
+#endif
+		*(.rodata)
+		*(".rodata.*")
+		*(.gnu.linkonce.r.*)
 	} GROUP_LINK_IN(RAMABLE_REGION)
 
 #include <linker/common-ram.ld>
@@ -91,17 +96,6 @@ SECTIONS
 	{
 
 		 . = ALIGN(4);
-		 KEEP(*(.isr_irq*))
-
-		 /* sections for IRQ0-9 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))
-
-		 /* sections for IRQ10-99 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
-
-		 /* sections for IRQ100-999 */
-		 KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
-
 		 *(.data)
 		 *(".data.*")
 
@@ -142,5 +136,9 @@ SECTIONS
 
      _end = .; /* end of image */
 
+#ifdef CONFIG_GEN_ISR_TABLES
+#include <linker/intlist.ld>
+#endif
+
      GROUP_END(RAMABLE_REGION)
 }