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| 1 | +/* |
| 2 | + * Copyright (c) 2025 MASSDRIVER EI (massdriver.space) |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#include <zephyr/kernel.h> |
| 8 | +#include <zephyr/drivers/pinctrl.h> |
| 9 | + |
| 10 | +#include <bflb_soc.h> |
| 11 | +#include <glb_reg.h> |
| 12 | +#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h> |
| 13 | + |
| 14 | +#if defined(CONFIG_SOC_SERIES_BL60X) |
| 15 | +#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h> |
| 16 | +#else |
| 17 | +#error "Unsupported Platform" |
| 18 | +#endif |
| 19 | + |
| 20 | +void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func) |
| 21 | +{ |
| 22 | + /* uart func for BL602 and BL702 Only*/ |
| 23 | + uint32_t regval; |
| 24 | + uint8_t sig; |
| 25 | + uint8_t sig_pos; |
| 26 | + |
| 27 | + regval = sys_read32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET); |
| 28 | + |
| 29 | + sig = pin % 8; |
| 30 | + sig_pos = sig << 2; |
| 31 | + |
| 32 | + regval &= (~(0x0f << sig_pos)); |
| 33 | + regval |= (func << sig_pos); |
| 34 | + |
| 35 | + for (uint8_t i = 0; i < 8; i++) { |
| 36 | + /* reset other sigs which are the same with uart_func */ |
| 37 | + sig_pos = i << 2; |
| 38 | + if (((regval & (0x0f << sig_pos)) == (func << sig_pos)) && (i != sig) && (func != |
| 39 | +0x0f)) { |
| 40 | + regval &= (~(0x0f << sig_pos)); |
| 41 | + regval |= (0x0f << sig_pos); |
| 42 | + } |
| 43 | + } |
| 44 | + |
| 45 | + sys_write32(regval, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET); |
| 46 | +} |
| 47 | + |
| 48 | +void pinctrl_bflb_init_pin(pinctrl_soc_pin_t pin) |
| 49 | +{ |
| 50 | + uint8_t drive; |
| 51 | + uint8_t function; |
| 52 | + uint16_t mode; |
| 53 | + uint32_t regval; |
| 54 | + uint8_t real_pin; |
| 55 | + uint8_t is_odd = 0; |
| 56 | + uint32_t cfg = 0; |
| 57 | + uint32_t cfg_address; |
| 58 | + |
| 59 | + real_pin = BFLB_PINMUX_GET_PIN(pin); |
| 60 | + function = BFLB_PINMUX_GET_FUN(pin); |
| 61 | + mode = BFLB_PINMUX_GET_MODE(pin); |
| 62 | + drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pin); |
| 63 | + |
| 64 | + /* Disable output anyway */ |
| 65 | + regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2)); |
| 66 | + regval &= ~(1 << (real_pin & 0x1f)); |
| 67 | + sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2)); |
| 68 | + |
| 69 | + is_odd = real_pin & 1; |
| 70 | + |
| 71 | + cfg_address = GLB_BASE + GLB_GPIO_CFGCTL0_OFFSET + (real_pin / 2 * 4); |
| 72 | + cfg = sys_read32(cfg_address); |
| 73 | + cfg &= ~(0xffff << (16 * is_odd)); |
| 74 | + |
| 75 | + regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2)); |
| 76 | + |
| 77 | + if (mode == BFLB_PINMUX_MODE_analog) { |
| 78 | + regval &= ~(1 << (real_pin & 0x1f)); |
| 79 | + function = 10; |
| 80 | + } else if (mode == BFLB_PINMUX_MODE_periph) { |
| 81 | + cfg |= (1 << (is_odd * 16 + 0)); |
| 82 | + regval &= ~(1 << (real_pin & 0x1f)); |
| 83 | + } else { |
| 84 | + function = 11; |
| 85 | + |
| 86 | + if (mode == BFLB_PINMUX_MODE_input) { |
| 87 | + cfg |= (1 << (is_odd * 16 + 0)); |
| 88 | + } |
| 89 | + |
| 90 | + if (mode == BFLB_PINMUX_MODE_output) { |
| 91 | + regval |= (1 << (real_pin & 0x1f)); |
| 92 | + } |
| 93 | + } |
| 94 | + |
| 95 | + sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2)); |
| 96 | + |
| 97 | + uint8_t pull_up = BFLB_PINMUX_GET_PULL_UP(pin); |
| 98 | + uint8_t pull_down = BFLB_PINMUX_GET_PULL_DOWN(pin); |
| 99 | + |
| 100 | + if (pull_up) { |
| 101 | + cfg |= (1 << (is_odd * 16 + 4)); |
| 102 | + } else if (pull_down) { |
| 103 | + cfg |= (1 << (is_odd * 16 + 5)); |
| 104 | + } else { |
| 105 | + } |
| 106 | + |
| 107 | + if (BFLB_PINMUX_GET_SMT(pin)) { |
| 108 | + cfg |= (1 << (is_odd * 16 + 1)); |
| 109 | + } |
| 110 | + |
| 111 | + cfg |= (drive << (is_odd * 16 + 2)); |
| 112 | + cfg |= (function << (is_odd * 16 + 8)); |
| 113 | + sys_write32(cfg, cfg_address); |
| 114 | +} |
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