bflb: Make BL60x independant from SDK

Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f

Signed-off-by: Camille BAUD <[email protected]>

Author: VynDragon

boards/aithinker/ai_wb2_12f/ai_wb2_12f.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <bflb/bl60x.dtsi>
+#include <bflb/bl602.dtsi>
 #include "ai_wb2_12f-pinctrl.dtsi"
 
 / {
@@ -15,6 +15,7 @@
 
 	chosen {
 		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
 		zephyr,itcm = &itcm;
 		zephyr,dtcm = &dtcm;
 		zephyr,sram = &sram0;
@@ -27,18 +28,30 @@
 	clock-frequency = <DT_FREQ_M(192)>;
 };
 
-&spi1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0x4000b000 0x1000 0x23000000 0x400000>;
-
-	flash0: flash@0 {
-		compatible = "zb,25vq32", "jedec,spi-nor";
-		status = "disabled";
-		size = <DT_SIZE_M(128)>;
-		jedec-id = [5e 40 16];
-		reg = <0>;
-		spi-max-frequency = <DT_FREQ_M(133)>;
+&flashctrl {
+	flash0: flash@23000000 {
+		compatible = "soc-nv-flash", "zb,25vq32";
+		reg = <0x23000000 (0x400000 - 0x2000)>;
+		write-block-size = <256>;
+		erase-block-size = <DT_SIZE_K(4)>;
+		/* jedec-id = [5e 40 16]; */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			slot0_partition: partition@0 {
+				label = "image-0";
+				reg = <0x00000000 0x00100000>;
+				read-only;
+			};
+
+			storage_partition: partition@100000 {
+				label = "storage";
+				reg = <0x00100000 (0x300000 - 0x2000)>;
+			};
+		};
 	};
 };
 

boards/aithinker/ai_wb2_12f/support/bl60x.cfg

@@ -38,23 +38,22 @@ echo "Ready for Remote Connections"
 
 $_TARGETNAME.0 configure -event reset-assert-pre {
     echo "reset-assert-pre"
-    adapter speed 100
+    adapter speed 400
 }
 
 $_TARGETNAME.0 configure -event reset-deassert-post {
     echo "reset-deassert-post"
 
-    adapter speed 100
+    adapter speed 400
 
-    reg mstatus 0x7800
-    reg mie 0x0
-#    reg pc 0x23000000
+    reg mstatus 0x0
+    reg pc 0x21000000
 }
 
 $_TARGETNAME.0 configure -event reset-init {
     echo "reset-init"
 
-    adapter speed 3000
+    adapter speed 400
 }
 
 $_TARGETNAME.0 configure -event gdb-attach {

boards/aithinker/ai_wb2_12f/support/openocd.cfg

@@ -2,4 +2,4 @@
 
 interface cmsis-dap
 
-adapter speed 1000
+adapter speed 400

boards/bflb/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts

@@ -6,7 +6,7 @@
 
 /dts-v1/;
 
-#include <bflb/bl60x.dtsi>
+#include <bflb/bl604.dtsi>
 #include "bl604e_iot_dvk-pinctrl.dtsi"
 
 / {
@@ -15,6 +15,7 @@
 
 	chosen {
 		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
 		zephyr,itcm = &itcm;
 		zephyr,dtcm = &dtcm;
 		zephyr,sram = &sram0;
@@ -27,18 +28,30 @@
 	clock-frequency = <DT_FREQ_M(192)>;
 };
 
-&spi1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0x4000b000 0x1000 0x23000000 0xc00000>;
-
-	flash0: flash@0 {
-		compatible = "issi,is25lp128", "jedec,spi-nor";
-		status = "disabled";
-		size = <DT_SIZE_M(128)>;
-		jedec-id = [96 60 18];
-		reg = <0>;
-		spi-max-frequency = <DT_FREQ_M(133)>;
+&flashctrl {
+	flash0: flash@23000000 {
+		compatible = "soc-nv-flash", "issi,is25lp128";
+		reg = <0x23000000 (0x1000000 - 0x2000)>;
+		write-block-size = <256>;
+		erase-block-size = <DT_SIZE_K(4)>;
+		/* jedec-id = [96 60 18]; */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			slot0_partition: partition@0 {
+				label = "image-0";
+				reg = <0x00000000 0x100000>;
+				read-only;
+			};
+
+			storage_partition: partition@100000 {
+				label = "storage";
+				reg = <0x00100000 (0xF00000 - 0x2000)>;
+			};
+		};
 	};
 };
 

boards/doiting/dt_bl10_devkit/dt_bl10_devkit.dts

@@ -14,6 +14,7 @@
 
 	chosen {
 		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
 		zephyr,itcm = &itcm;
 		zephyr,dtcm = &dtcm;
 		zephyr,sram = &sram0;
@@ -26,18 +27,30 @@
 	clock-frequency = <DT_FREQ_M(192)>;
 };
 
-&spi1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0x4000b000 0x1000 0x23000000 0xc00000>;
-
-	flash0: flash@0 {
-		compatible = "issi,is25lp128", "jedec,spi-nor";
-		status = "disabled";
-		size = <DT_SIZE_M(128)>;
-		jedec-id = [96 60 18];
-		reg = <0>;
-		spi-max-frequency = <DT_FREQ_M(133)>;
+&flashctrl {
+	flash0: flash@23000000 {
+		compatible = "soc-nv-flash", "issi,is25lp128";
+		reg = <0x23000000 (0x1000000 - 0x2000)>;
+		write-block-size = <256>;
+		erase-block-size = <DT_SIZE_K(4)>;
+		/* jedec-id = [96 60 18]; */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			slot0_partition: partition@0 {
+				label = "image-0";
+				reg = <0x00000000 0x100000>;
+				read-only;
+			};
+
+			storage_partition: partition@100000 {
+				label = "storage";
+				reg = <0x00100000 (0xF00000 - 0x2000)>;
+			};
+		};
 	};
 };
 

drivers/pinctrl/CMakeLists.txt

@@ -10,7 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS2 pinctrl_arm_mps2.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS3 pinctrl_arm_mps3.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS4 pinctrl_arm_mps4.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_V2M_BEETLE pinctrl_arm_v2m_beetle.c)
-zephyr_library_sources_ifdef(CONFIG_PINCTRL_BFLB pinctrl_bflb.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
@@ -59,3 +58,8 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_00X_AFIO pinctrl_wch_00x_afio.c)
 
 add_subdirectory(renesas)
+
+if (CONFIG_PINCTRL_BFLB)
+  zephyr_library_sources(pinctrl_bflb.c)
+  zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_BL60X pinctrl_bflb_bl60x_70x.c)
+endif()

drivers/pinctrl/pinctrl_bflb.c

@@ -6,40 +6,35 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/pinctrl.h>
-#include <bflb_pinctrl.h>
-#include <bflb_glb.h>
-#include <bflb_gpio.h>
 
-/* clang-format off */
+#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
 
-int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
-			   uintptr_t reg)
+#if defined(CONFIG_SOC_SERIES_BL60X)
+#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
+#else
+#error "Unsupported Platform"
+#endif
+
+void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func);
+void pinctrl_bflb_init_pin(pinctrl_soc_pin_t pin);
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
 {
-	GLB_GPIO_Cfg_Type pincfg;
 	uint8_t i;
 
 	ARG_UNUSED(reg);
 
 	for (i = 0U; i < pin_cnt; i++) {
-		pincfg.gpioFun  = BFLB_PINMUX_GET_FUN(pins[i]);
-		pincfg.gpioMode = BFLB_PINMUX_GET_MODE(pins[i]);
-		pincfg.gpioPin  = BFLB_PINMUX_GET_PIN(pins[i]);
-		pincfg.pullType = BFLB_PINMUX_GET_PULL_MODES(pins[i]);
-		pincfg.smtCtrl  = BFLB_PINMUX_GET_SMT(pins[i]);
-		pincfg.drive    = BFLB_PINMUX_GET_DRIVER_STRENGTH(pins[i]);
-
-		if (pincfg.gpioFun == BFLB_PINMUX_FUN_INST_uart0) {
-			GLB_UART_Fun_Sel(pincfg.gpioPin % 8,
-					 (BFLB_PINMUX_GET_INST(pins[i]))
-					  * 0x4U /* rts, cts, rx, tx */
-					  + BFLB_PINMUX_GET_SIGNAL(pins[i])
-					 );
+
+		if ((BFLB_PINMUX_GET_FUN(pins[i]) & BFLB_PINMUX_FUN_MASK)
+			== BFLB_PINMUX_FUN_INST_uart0) {
+			pinctrl_bflb_configure_uart(BFLB_PINMUX_GET_PIN(pins[i]),
+			BFLB_PINMUX_GET_SIGNAL(pins[i]) + 4 * BFLB_PINMUX_GET_INST(pins[i]));
 		}
 
-		GLB_GPIO_Init(&pincfg);
+		/* gpio init*/
+		pinctrl_bflb_init_pin(pins[i]);
 	}
 
 	return 0;
 }
-
-/* clang-format on */

drivers/pinctrl/pinctrl_bflb_bl60x_70x.c

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#include <bflb_soc.h>
+#include <glb_reg.h>
+#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
+
+#if defined(CONFIG_SOC_SERIES_BL60X)
+#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
+#else
+#error "Unsupported Platform"
+#endif
+
+void pinctrl_bflb_configure_uart(uint8_t pin, uint8_t func)
+{
+	/* uart func for BL602 and BL702 Only*/
+	uint32_t regval;
+	uint8_t sig;
+	uint8_t sig_pos;
+
+	regval = sys_read32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
+
+	sig = pin % 8;
+	sig_pos = sig << 2;
+
+	regval &= (~(0x0f << sig_pos));
+	regval |= (func << sig_pos);
+
+	for (uint8_t i = 0; i < 8; i++) {
+		/* reset other sigs which are the same with uart_func */
+		sig_pos = i << 2;
+		if (((regval & (0x0f << sig_pos)) == (func << sig_pos)) && (i != sig) && (func !=
+0x0f)) {
+			regval &= (~(0x0f << sig_pos));
+			regval |= (0x0f << sig_pos);
+		}
+	}
+
+	sys_write32(regval, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
+}
+
+void pinctrl_bflb_init_pin(pinctrl_soc_pin_t pin)
+{
+	uint8_t drive;
+	uint8_t function;
+	uint16_t mode;
+	uint32_t regval;
+	uint8_t real_pin;
+	uint8_t is_odd = 0;
+	uint32_t cfg = 0;
+	uint32_t cfg_address;
+
+	real_pin = BFLB_PINMUX_GET_PIN(pin);
+	function = BFLB_PINMUX_GET_FUN(pin);
+	mode = BFLB_PINMUX_GET_MODE(pin);
+	drive = BFLB_PINMUX_GET_DRIVER_STRENGTH(pin);
+
+	/* Disable output anyway */
+	regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
+	regval &= ~(1 << (real_pin & 0x1f));
+	sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
+
+	is_odd = real_pin & 1;
+
+	cfg_address = GLB_BASE + GLB_GPIO_CFGCTL0_OFFSET + (real_pin / 2 * 4);
+	cfg = sys_read32(cfg_address);
+	cfg &= ~(0xffff << (16 * is_odd));
+
+	regval = sys_read32(GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
+
+	if (mode == BFLB_PINMUX_MODE_analog) {
+		regval &= ~(1 << (real_pin & 0x1f));
+		function = 10;
+	} else if (mode == BFLB_PINMUX_MODE_periph) {
+		cfg |= (1 << (is_odd * 16 + 0));
+		regval &= ~(1 << (real_pin & 0x1f));
+	} else {
+		function = 11;
+
+		if (mode == BFLB_PINMUX_MODE_input) {
+			cfg |= (1 << (is_odd * 16 + 0));
+		}
+
+		if (mode == BFLB_PINMUX_MODE_output) {
+			regval |= (1 << (real_pin & 0x1f));
+		}
+	}
+
+	sys_write32(regval, GLB_BASE + GLB_GPIO_CFGCTL34_OFFSET + ((real_pin >> 5) << 2));
+
+	uint8_t pull_up = BFLB_PINMUX_GET_PULL_UP(pin);
+	uint8_t pull_down = BFLB_PINMUX_GET_PULL_DOWN(pin);
+
+	if (pull_up) {
+		cfg |= (1 << (is_odd * 16 + 4));
+	} else if (pull_down) {
+		cfg |= (1 << (is_odd * 16 + 5));
+	} else {
+	}
+
+	if (BFLB_PINMUX_GET_SMT(pin)) {
+		cfg |= (1 << (is_odd * 16 + 1));
+	}
+
+	cfg |= (drive << (is_odd * 16 + 2));
+	cfg |= (function << (is_odd * 16 + 8));
+	sys_write32(cfg, cfg_address);
+}