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soc: atmel_sam0: Add support for SAMR34 and SAMR35 parts
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34 Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO, PWM, ADC. NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt, but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet is incorrect (the ADC doesn't function with line 20), and as such, I have also omitted the adjustments for TC4 and AC... Signed-off-by: Attie Grande <[email protected]>
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‎dts/arm/atmel/samr34.dtsi‎

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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <freq.h>
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#include <atmel/saml21.dtsi>
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#include <dt-bindings/lora/sx126x.h>
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#include "saml21.dtsi"
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/ {
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aliases {
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lora0 = &lora;
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};
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soc {
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pinctrl@40002800 {
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ranges = <0x40002800 0x40002800 0x180>;
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portc: gpio@40002900 {
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compatible = "atmel,sam0-gpio";
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reg = <0x40002900 0x80>;
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label = "PORTC";
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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};
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};
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};
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/delete-node/ &dac;
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&sercom4 {
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/* SERCOM4 is used to interface with the internal LoRa radio */
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compatible = "atmel,sam0-spi";
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dipo = <0>;
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dopo = <1>;
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cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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lora: sx1276@0 {
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compatible = "semtech,sx1276";
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reg = <0>;
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label = "SX1276";
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reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; /* nRST */
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dio-gpios =
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<&portb 16 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 */
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<&porta 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 */
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<&porta 12 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 */
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<&portb 17 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 */
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<&porta 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 */
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<&portb 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 */
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spi-max-frequency = <DT_FREQ_M(10)>;
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};
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};

‎dts/arm/atmel/samr35.dtsi‎

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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <atmel/samr34.dtsi>
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/delete-node/ &usb0;

‎soc/arm/atmel_sam0/common/CMakeLists.txt‎

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@@ -11,6 +11,8 @@ zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAML21 soc_saml2x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR34 soc_saml2x.c soc_samr34.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR35 soc_saml2x.c soc_samr34.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD51 soc_samd5x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAME51 soc_samd5x.c)

‎soc/arm/atmel_sam0/common/Kconfig.saml2x‎

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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_SAML21
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if SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
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config SOC_ATMEL_SAML_DEBUG_PAUSE
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bool "Insert a pause at boot, to allow a debugger to attach"
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endchoice
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endif # SOC_SERIES_SAML21
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endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35

‎soc/arm/atmel_sam0/common/soc_samr34.c‎

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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <soc.h>
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#if !(ATMEL_SAM0_DT_SERCOM_CHECK(4, atmel_sam0_spi) && CONFIG_SPI_SAM0)
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/* When the radio is not in use, it's important that #CS is set high, to avoid
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* unexpected behavior and increased current consumption... see Chapter 10 of
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* DS70005356C. We also hold the radio in reset.
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*/
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static int soc_pinconf_init(const struct device *dev)
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{
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const struct device *portb = DEVICE_DT_GET(DT_NODELABEL(portb));
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ARG_UNUSED(dev);
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if (!device_is_ready(portb)) {
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return -ENODEV;
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}
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gpio_pin_configure(portb, 31, GPIO_OUTPUT_HIGH);
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gpio_pin_configure(portb, 15, GPIO_OUTPUT_LOW);
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return 0;
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}
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SYS_INIT(soc_pinconf_init, PRE_KERNEL_2, 0);
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#endif

‎soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series‎

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# Atmel SAML MCU series configuration options
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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_SAMR34
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config SOC_SERIES
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default "samr34"
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config SOC_PART_NUMBER
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default "samr34j16b" if SOC_PART_NUMBER_SAMR34J16B
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default "samr34j17b" if SOC_PART_NUMBER_SAMR34J17B
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default "samr34j18b" if SOC_PART_NUMBER_SAMR34J18B
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config NUM_IRQS
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default 23
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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endif # SOC_SERIES_SAMR34

‎soc/arm/atmel_sam0/samr34/Kconfig.series‎

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# Atmel SAMR34 MCU series
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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_SAMR34
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bool "Atmel SAMR34 MCU"
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select ARM
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select CPU_CORTEX_M0PLUS
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select SOC_FAMILY_SAM0
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select ASF
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help
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Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers.

‎soc/arm/atmel_sam0/samr34/Kconfig.soc‎

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# Atmel SAMR MCU series
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# Copyright (c) 2021 Argentum Systems Ltd.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Atmel SAMR34 MCU Selection"
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depends on SOC_SERIES_SAMR34
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config SOC_PART_NUMBER_SAMR34J16B
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bool "SAMR34J16B"
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config SOC_PART_NUMBER_SAMR34J17B
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bool "SAMR34J17B"
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config SOC_PART_NUMBER_SAMR34J18B
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bool "SAMR34J18B"
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endchoice

‎soc/arm/atmel_sam0/samr34/linker.ld‎

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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2021 Argentum Systems Ltd.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

‎soc/arm/atmel_sam0/samr34/soc.h‎

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/* Copyright (c) 2021 Argentum Systems Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ATMEL_SAMR_SOC_H_
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#define _ATMEL_SAMR_SOC_H_
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#ifndef _ASMLANGUAGE
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#define DONT_USE_CMSIS_INIT
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#include <zephyr/types.h>
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#if defined(CONFIG_SOC_PART_NUMBER_SAMR34J16B)
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#include <samr34j16b.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J17B)
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#include <samr34j17b.h>
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#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J18B)
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#include <samr34j18b.h>
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#else
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#error Library does not support the specified device.
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#endif
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#endif /* _ASMLANGUAGE */
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#include "adc_fixup_sam0.h"
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#include "../common/soc_port.h"
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#include "../common/atmel_sam0_dt.h"
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/** Processor Clock (HCLK) Frequency */
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#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ
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/** Master Clock (MCK) Frequency */
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#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
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#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
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#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000
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#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000
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#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0
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#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
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#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN)
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#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ
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#else
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#error Unsupported GCLK1 clock source.
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#endif
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#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
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#endif /* _ATMEL_SAMR_SOC_H_ */

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