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drivers: serial: npcx: add serial driver support for npck3
This commit adds serial driver support for npck3. Signed-off-by: Alvis Sun <[email protected]> Signed-off-by: Tom Chang <[email protected]> Signed-off-by: Mulin Chao <[email protected]>
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4 files changed

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drivers/serial/Kconfig.npcx

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,10 @@ config UART_NPCX_USE_MDMA
2525
select SERIAL_SUPPORT_ASYNC
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help
2727
Enable support for npcx UART DMA mode.
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29+
config UART_NPCX_FIFO_EX
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bool "Extended NPCX UART FIFO driver support"
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default y if DT_HAS_NUVOTON_NPCX_UART_NPCKN_ENABLED
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help
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This option enables the extended UART FIFO driver for NPCKN variant
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of processors.

drivers/serial/uart_npcx.c

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -167,7 +167,11 @@ static int uart_npcx_rx_fifo_available(const struct device *dev)
167167
struct uart_reg *const inst = config->inst;
168168

169169
/* True if at least one byte is in the Rx FIFO */
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#if defined(CONFIG_UART_NPCX_FIFO_EX)
171+
return inst->URXFLV != 0;
172+
#else
170173
return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);
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#endif
171175
}
172176

173177
static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
@@ -176,8 +180,12 @@ static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
176180
struct uart_reg *const inst = config->inst;
177181

178182
/* Disable all Tx interrupts */
183+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
184+
inst->UICTRL &= ~BIT(NPCX_UICTRL_ETI);
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#else
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inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | BIT(NPCX_UFTCTL_TEMPTY_EN) |
180187
BIT(NPCX_UFTCTL_NXMIP_EN));
188+
#endif
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}
182190

183191
static void uart_npcx_clear_rx_fifo(const struct device *dev)
@@ -201,7 +209,11 @@ static int uart_npcx_tx_fifo_ready(const struct device *dev)
201209
struct uart_reg *const inst = config->inst;
202210

203211
/* True if the Tx FIFO is not completely full */
212+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
213+
return inst->UTXFLV != NPCK_SZ_UART_FIFO;
214+
#else
204215
return !(GET_FIELD(inst->UFTSTS, NPCX_UFTSTS_TEMPTY_LVL) == 0);
216+
#endif
205217
}
206218

207219
static int uart_npcx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
@@ -246,30 +258,44 @@ static void uart_npcx_irq_tx_enable(const struct device *dev)
246258
{
247259
const struct uart_npcx_config *const config = dev->config;
248260
struct uart_reg *const inst = config->inst;
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#if defined(CONFIG_UART_NPCX_FIFO_EX)
263+
inst->UICTRL |= BIT(NPCX_UICTRL_ETI);
264+
#else
249265
struct uart_npcx_data *data = dev->data;
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k_spinlock_key_t key = k_spin_lock(&data->lock);
251267

252268
inst->UFTCTL |= BIT(NPCX_UFTCTL_TEMPTY_EN);
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k_spin_unlock(&data->lock, key);
270+
#endif
254271
}
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256273
static void uart_npcx_irq_tx_disable(const struct device *dev)
257274
{
258275
const struct uart_npcx_config *const config = dev->config;
259276
struct uart_reg *const inst = config->inst;
277+
278+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
279+
inst->UICTRL &= ~(BIT(NPCX_UICTRL_ETI));
280+
#else
260281
struct uart_npcx_data *data = dev->data;
261282
k_spinlock_key_t key = k_spin_lock(&data->lock);
262283

263284
inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_EN));
264285
k_spin_unlock(&data->lock, key);
286+
#endif
265287
}
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267289
static bool uart_npcx_irq_tx_is_enabled(const struct device *dev)
268290
{
269291
const struct uart_npcx_config *const config = dev->config;
270292
struct uart_reg *const inst = config->inst;
271293

294+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
295+
return IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_ETI);
296+
#else
272297
return IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_TEMPTY_EN);
298+
#endif
273299
}
274300

275301
static int uart_npcx_irq_tx_ready(const struct device *dev)
@@ -283,31 +309,47 @@ static int uart_npcx_irq_tx_complete(const struct device *dev)
283309
struct uart_reg *const inst = config->inst;
284310

285311
/* Tx FIFO is empty or last byte is sending */
312+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
313+
return inst->UTXFLV == 0;
314+
#else
286315
return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);
316+
#endif
287317
}
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289319
static void uart_npcx_irq_rx_enable(const struct device *dev)
290320
{
291321
const struct uart_npcx_config *const config = dev->config;
292322
struct uart_reg *const inst = config->inst;
293323

324+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
325+
inst->UICTRL |= BIT(NPCX_UICTRL_ERI);
326+
#else
294327
inst->UFRCTL |= BIT(NPCX_UFRCTL_RNEMPTY_EN);
328+
#endif
295329
}
296330

297331
static void uart_npcx_irq_rx_disable(const struct device *dev)
298332
{
299333
const struct uart_npcx_config *const config = dev->config;
300334
struct uart_reg *const inst = config->inst;
301335

336+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
337+
inst->UICTRL &= ~(BIT(NPCX_UICTRL_ERI));
338+
#else
302339
inst->UFRCTL &= ~(BIT(NPCX_UFRCTL_RNEMPTY_EN));
340+
#endif
303341
}
304342

305343
static bool uart_npcx_irq_rx_is_enabled(const struct device *dev)
306344
{
307345
const struct uart_npcx_config *const config = dev->config;
308346
struct uart_reg *const inst = config->inst;
309347

348+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
349+
return IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_ERI);
350+
#else
310351
return IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN);
352+
#endif
311353
}
312354

313355
static int uart_npcx_irq_rx_ready(const struct device *dev)
@@ -895,6 +937,7 @@ static void uart_npcx_isr(const struct device *dev)
895937
}
896938
#endif
897939

940+
#if !defined(CONFIG_UART_NPCX_FIFO_EX)
898941
#if defined(CONFIG_PM) || defined(CONFIG_UART_ASYNC_API)
899942
if (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_NXMIP_EN) &&
900943
IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP)) {
@@ -915,6 +958,7 @@ static void uart_npcx_isr(const struct device *dev)
915958
#endif
916959
}
917960
#endif
961+
#endif
918962
}
919963
#endif
920964

@@ -1060,8 +1104,12 @@ static int uart_npcx_init(const struct device *dev)
10601104

10611105
/* Initialize UART FIFO if mode is interrupt driven */
10621106
#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
1107+
#if defined(CONFIG_UART_NPCX_FIFO_EX)
1108+
inst->UFCTRL |= BIT(NPCK_FIFO_EN);
1109+
#else
10631110
/* Enable the UART FIFO mode */
10641111
inst->UMDSL |= BIT(NPCX_UMDSL_FIFO_MD);
1112+
#endif
10651113

10661114
/* Disable all UART tx FIFO interrupts */
10671115
uart_npcx_dis_all_tx_interrupts(dev);

dts/arm/nuvoton/npck/npck3.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
};
5454

5555
uart1: serial@400c4000 {
56-
compatible = "nuvoton,npcx-uart";
56+
compatible = "nuvoton,npcx-uart", "nuvoton,npcx-uart-npckn";
5757
reg = <0x400C4000 0x2000>;
5858
interrupts = <23 3>;
5959
clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL1 4>;
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
# Copyright (c) 2025 Nuvoton Technology Corporation.
2+
# SPDX-License-Identifier: Apache-2.0
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4+
description: |
5+
Nuvoton npcx serial uart for npckn variant
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7+
compatible: "nuvoton,npcx-uart-npckn"
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include: nuvoton,npcx-uart.yaml

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