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intel_adsp: Introduce ACE 4.0 architecture with NVL/NVL-S platforms
Introduce the ACE 4.0 architecture, along with support for the NVL and NVL-S platforms within the Intel ADSP framework in the Zephyr project. This update includes: - Addition of ACE 4.0 architecture configurations in Kconfig and Kconfig.intel_adsp. - Inclusion of device tree source files for NVL and NVL-S platforms, defining CPU, memory, and peripheral configurations. - Updates to driver files to support ACE 4.0 specific features, including DMIC and SSP configurations. - Introduction of new header files for ACE 4.0, detailing boot, interrupt, IPC, power, and shim functionalities. - Modifications to the CMakeLists.txt to include ACE 4.0 MMU support. - Addition of default configurations for NVL and NVL-S platforms in Kconfig.defconfig.ace40. The NVL and NVL-S platforms are part of the Nova Lake series, targeting advanced audio processing capabilities. ACE 4.0 introduces enhanced DSP capabilities and advanced power management features, improving audio stream handling and synchronization compared to ACE 3.0. Signed-off-by: Flavio Ceolin <[email protected]> Signed-off-by: Daniel Leung <[email protected]> Signed-off-by: Serhiy Katsyuba <[email protected]> Signed-off-by: Anas Nashif <[email protected]> Signed-off-by: Tomasz Leman <[email protected]>
1 parent 3fc27e7 commit bfdab16

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+1702
-12
lines changed

‎boards/intel/adsp/Kconfig

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@@ -10,3 +10,4 @@ config RIMAGE_TARGET
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default "lnl" if BOARD_INTEL_ADSP_ACE20_LNL || BOARD_INTEL_ADSP_ACE20_LNL_SIM
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default "ptl" if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM
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default "wcl" if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM
13+
default "nvl" if BOARD_INTEL_ADSP_ACE40_NVL || BOARD_INTEL_ADSP_ACE40_NVL_SIM || BOARD_INTEL_ADSP_ACE40_NVLS

‎boards/intel/adsp/Kconfig.intel_adsp

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@@ -12,3 +12,6 @@ config BOARD_INTEL_ADSP
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM
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select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL
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select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVL_SIM
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select SOC_INTEL_ACE40 if BOARD_INTEL_ADSP_ACE40_NVLS

‎boards/intel/adsp/board.yml

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@@ -20,3 +20,9 @@ boards:
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- name: 'wcl'
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variants:
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- name: 'sim'
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- name: ace40
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variants:
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- name: 'nvl'
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variants:
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- name: 'sim'
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- name: 'nvls'

‎boards/intel/adsp/intel_adsp_ace40_nvl.dts

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@@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <intel/intel_adsp_ace40_nvl.dtsi>
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/ {
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model = "intel_adsp_ace40_nvl";
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compatible = "intel";
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &mem_window3;
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};
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};

‎boards/intel/adsp/intel_adsp_ace40_nvl_defconfig

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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=4096
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
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CONFIG_DCACHE_LINE_SIZE=64

‎boards/intel/adsp/intel_adsp_ace40_nvl_sim_defconfig

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@@ -0,0 +1,14 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_INTEL_ADSP_SIM=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
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CONFIG_DCACHE_LINE_SIZE=64

‎boards/intel/adsp/intel_adsp_ace40_nvls.dts

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@@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <intel/intel_adsp_ace40_nvls.dtsi>
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/ {
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model = "intel_adsp_ace40_nvls";
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compatible = "intel";
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &mem_window3;
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};
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};

‎boards/intel/adsp/intel_adsp_ace40_nvls_defconfig

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@@ -0,0 +1,12 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=4096
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
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CONFIG_DCACHE_LINE_SIZE=64

‎boards/intel/adsp/twister.yaml

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@@ -56,6 +56,23 @@ variants:
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- zephyr
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testing:
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timeout_multiplier: 8
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intel_adsp/ace40/nvls:
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toolchain:
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- xt-clang
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intel_adsp/ace40/nvl:
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toolchain:
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- xt-clang
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intel_adsp/ace40/nvl/sim:
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type: sim
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toolchain:
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- xt-clang
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simulation:
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- name: custom
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exec: acesim
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testing:
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timeout_multiplier: 8
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intel_adsp/ace40:
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twister: false
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intel_adsp/cavs25:
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toolchain:
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- xcc

‎drivers/dai/intel/dmic/dmic.c

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Original file line numberDiff line numberDiff line change
@@ -162,7 +162,8 @@ static inline void dai_dmic_release_ownership(const struct dai_intel_dmic *dmic)
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static inline uint32_t dai_dmic_base(const struct dai_intel_dmic *dmic)
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{
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#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
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#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
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defined(CONFIG_SOC_INTEL_ACE40)
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return dmic->hdamldmic_base;
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#else
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return dmic->shim_base;
@@ -175,7 +176,8 @@ static inline void dai_dmic_set_sync_period(uint32_t period, const struct dai_in
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uint32_t val = CONFIG_DAI_DMIC_HW_IOCLK / period - 1;
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uint32_t base = dai_dmic_base(dmic);
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/* DMIC Change sync period */
178-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
179+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
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defined(CONFIG_SOC_INTEL_ACE40)
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sys_write32(sys_read32(base + DMICSYNC_OFFSET) | FIELD_PREP(DMICSYNC_SYNCPRD, val),
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base + DMICSYNC_OFFSET);
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sys_write32(sys_read32(base + DMICSYNC_OFFSET) | DMICSYNC_SYNCPU,
@@ -262,7 +264,8 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
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static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
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{
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/* Disable DMIC clock gating */
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#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
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#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
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defined(CONFIG_SOC_INTEL_ACE40)
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sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) | DMICLVSCTL_DCGD),
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dmic->vshim_base + DMICLVSCTL_OFFSET);
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#else
@@ -274,7 +277,8 @@ static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
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static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
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{
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/* Enable DMIC clock gating */
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#if (CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30)
280+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
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defined(CONFIG_SOC_INTEL_ACE40)
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sys_write32((sys_read32(dmic->vshim_base + DMICLVSCTL_OFFSET) & ~DMICLVSCTL_DCGD),
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dmic->vshim_base + DMICLVSCTL_OFFSET);
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#else /* All other CAVS and ACE platforms */
@@ -288,7 +292,8 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
288292
const struct dai_config *cfg,
289293
uint32_t index)
290294
{
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#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
295+
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
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defined(CONFIG_SOC_INTEL_ACE40)
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uint16_t pcmsycm = cfg->link_config;
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uint32_t reg_add = dmic->shim_base + DMICXPCMSyCM_OFFSET + 0x0004*index;
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@@ -297,7 +302,7 @@ static inline void dai_dmic_program_channel_map(const struct dai_intel_dmic *dmi
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ARG_UNUSED(dmic);
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ARG_UNUSED(cfg);
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ARG_UNUSED(index);
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#endif /* defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) */
305+
#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 */
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}
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static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
@@ -307,7 +312,8 @@ static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
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sys_write32((sys_read32(base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
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base + DMICLCTL_OFFSET);
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310-
#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30)
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#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) || \
316+
defined(CONFIG_SOC_INTEL_ACE40)
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while (!(sys_read32(base + DMICLCTL_OFFSET) & DMICLCTL_CPA)) {
312318
k_sleep(K_USEC(100));
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}

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