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soc: renesas: ra: Add support Renesas RA8T2 SoC
Add support Renesas RA8M2 SoC Signed-off-by: Khoa Tran <[email protected]>
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‎soc/renesas/ra/ra8t2/CMakeLists.txt‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_PM
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power.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra8t2/Kconfig‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA8T2
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select ARM
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select FPU
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select CPU_CORTEX_M_HAS_DWT
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select ARMV8_M_DSP
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select HAS_SWO
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select XIP
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select HAS_RENESAS_RA_FSP
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select SOC_EARLY_INIT_HOOK
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select HAS_PM
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config SOC_R7KA8T2LFECAC_CM85
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select CPU_CORTEX_M85
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select GPIO_RA_HAS_VBTICTLR
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config SOC_R7KA8T2LFECAC_CM33
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select CPU_CORTEX_M33
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select SOC_RA_SECOND_CORE_BUILD

‎soc/renesas/ra/ra8t2/Kconfig.defconfig‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA8T2
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config NUM_IRQS
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default 96
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DT_CPUCLK0_PATH := $(dt_nodelabel_path,cpuclk0)
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DT_CPUCLK1_PATH := $(dt_nodelabel_path,cpuclk1)
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DT_LOCO_PATH := $(dt_nodelabel_path,loco)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,$(DT_CPUCLK0_PATH),clock-frequency) if SOC_R7KA8T2LFECAC_CM85 && CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_CPUCLK1_PATH),clock-frequency) if SOC_R7KA8T2LFECAC_CM33 && CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
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config CORTEX_M_SYSTICK
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default n if RENESAS_RA_ULPT_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 4096 if RENESAS_RA_ULPT_TIMER
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config PM_DEVICE
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default y if PM
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config PM_STATS
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default n if PM
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config BUILD_OUTPUT_HEX
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default y
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config CLOCK_CONTROL
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default y
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config DCACHE
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default n
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config CACHE_MANAGEMENT
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default n
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endif # SOC_SERIES_RA8T2

‎soc/renesas/ra/ra8t2/Kconfig.soc‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA8T2
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA8T2 series
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config SOC_R7KA8T2LFECAC
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bool
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select SOC_SERIES_RA8T2
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help
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R7KA8T2LFECAC
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config SOC_R7KA8T2LFECAC_CM85
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bool
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select SOC_R7KA8T2LFECAC
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config SOC_R7KA8T2LFECAC_CM33
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bool
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select SOC_R7KA8T2LFECAC
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config SOC_SERIES
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default "ra8t2" if SOC_SERIES_RA8T2
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config SOC
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default "r7ka8t2lfecac" if SOC_R7KA8T2LFECAC

‎soc/renesas/ra/ra8t2/power.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <r_lpm.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/* Low Power Mode instance control structure */
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static lpm_instance_ctrl_t pm_state_ctrl;
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/* Configuration for Runtime Idle Power State */
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const lpm_cfg_t pm_state_runtime_idle_cfg = {
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.low_power_mode = LPM_MODE_SLEEP,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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/* Configuration for Standby Power State */
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const lpm_cfg_t pm_state_standby_cfg = {
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.low_power_mode = LPM_MODE_STANDBY,
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.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
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.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
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.io_port_state = LPM_IO_PORT_NO_CHANGE,
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.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
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.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
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.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
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.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
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.ram_retention_cfg.tcm_retention = true,
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.ldo_standby_cfg.pll1_ldo = false,
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.ldo_standby_cfg.pll2_ldo = false,
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.ldo_standby_cfg.hoco_ldo = false,
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.p_extend = NULL,
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};
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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R_LPM_Open(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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case PM_STATE_STANDBY:
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R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
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__disable_irq();
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__set_BASEPRI(0);
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__ISB();
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R_LPM_LowPowerModeEnter(&pm_state_ctrl);
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__enable_irq();
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__ISB();
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break;
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default:
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break;
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}
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}
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_RUNTIME_IDLE:
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__fallthrough;
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case PM_STATE_STANDBY:
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R_LPM_Close(&pm_state_ctrl);
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break;
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default:
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break;
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}
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irq_unlock(0);
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}

‎soc/renesas/ra/ra8t2/ram_sections.ld‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#ifdef CONFIG_USE_RA_FSP_DTC
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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#endif /* CONFIG_USE_RA_FSP_DTC */

‎soc/renesas/ra/ra8t2/sections.ld‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs0))
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SECTION_DATA_PROLOGUE(.option_setting_ofs0, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs0)),)
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{
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KEEP(*(.option_setting_ofs0))
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} GROUP_LINK_IN(OFS_OFS0_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs2))
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SECTION_DATA_PROLOGUE(.option_setting_ofs2, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs2)),)
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{
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KEEP(*(.option_setting_ofs2))
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} GROUP_LINK_IN(OFS_OFS2_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
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SECTION_DATA_PROLOGUE(.option_setting_sas, DT_REG_ADDR(DT_NODELABEL(option_setting_sas)),)
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{
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KEEP(*(.option_setting_sas))
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} GROUP_LINK_IN(OFS_SAS_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sec))
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SECTION_DATA_PROLOGUE(.option_setting_ofs1_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sec)),)
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{
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KEEP(*(.option_setting_ofs1_sec))
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} GROUP_LINK_IN(OFS_OFS1_SEC_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sec))
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SECTION_DATA_PROLOGUE(.option_setting_ofs3_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sec)),)
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{
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KEEP(*(.option_setting_ofs3_sec))
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} GROUP_LINK_IN(OFS_OFS3_SEC_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs1_sel))
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SECTION_DATA_PROLOGUE(.option_setting_ofs1_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs1_sel)),)
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{
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KEEP(*(.option_setting_ofs1_sel))
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} GROUP_LINK_IN(OFS_OFS1_SEL_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs3_sel))
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SECTION_DATA_PROLOGUE(.option_setting_ofs3_sel, DT_REG_ADDR(DT_NODELABEL(option_setting_ofs3_sel)),)
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{
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KEEP(*(.option_setting_ofs3_sel))
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} GROUP_LINK_IN(OFS_OFS3_SEL_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_bps_sec))
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SECTION_DATA_PROLOGUE(.option_setting_bps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_bps_sec)),)
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{
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KEEP(*(.option_setting_bps_sec))
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} GROUP_LINK_IN(OFS_BPS_SEC_MEMORY)
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#endif
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_otp_pbps_sec))
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SECTION_DATA_PROLOGUE(.option_setting_otp_pbps_sec, DT_REG_ADDR(DT_NODELABEL(option_setting_otp_pbps_sec)),)
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{
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KEEP(*(.option_setting_otp_pbps_sec))
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} GROUP_LINK_IN(OFS_OTP_PBPS_SEC_MEMORY)
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#endif

‎soc/renesas/ra/ra8t2/soc.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RA8T2 family processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/cache.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#include "soc.h"
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#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk)
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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extern volatile uint16_t g_protect_counters[];
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for (uint32_t i = 0; i < 5; i++) {
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g_protect_counters[i] = 0;
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}
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SystemCoreClock = BSP_MOCO_HZ;
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#ifdef CONFIG_CPU_CORTEX_M85
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#ifdef CONFIG_ICACHE
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SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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#endif
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#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT)
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/* Apply Arm Cortex-M85 errata workarounds for D-Cache
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* Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
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* Set bit 16 in ACTLR to 1.
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* See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641
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* Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0,
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* Document ID: SDEN-2236668).
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*/
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MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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ICB->ACTLR |= (1U << 16U);
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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sys_cache_data_enable();
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#endif
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#endif /*CONFIG_CPU_CORTEX_M85*/
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#ifdef CONFIG_CPU_CORTEX_M33
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#if FSP_PRIV_TZ_USE_SECURE_REGS
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/* Disable protection using PRCR register. */
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R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
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/* Initialize peripherals to secure mode for flat projects */
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R_PSCU->PSARB = 0;
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R_PSCU->PSARC = 0;
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R_PSCU->PSARD = 0;
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R_PSCU->PSARE = 0;
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R_CPSCU->ICUSARG = 0;
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R_CPSCU->ICUSARH = 0;
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R_CPSCU->ICUSARI = 0;
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/* Enable protection using PRCR register. */
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R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
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#endif
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#endif /*CONFIG_CPU_CORTEX_M33*/
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}

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