Skip to content

Commit c0e5769

Browse files
danieldegrassefabiobaltieri
authored andcommitted
drivers: mipi_dbi: mipi_dbi_nxp_lcdic: allow config of timer bases
The NXP LCDIC peripheral contains two internal timers, with configurable periods. These times are used to determine delays within the peripheral, such as the reset and tearing enable signal delays. Allow these periods to be set within the devicetree for the peripheral. Raise the period where required for display drivers that need a value other than the reset setting Signed-off-by: Daniel DeGrasse <[email protected]>
1 parent 2e66ce1 commit c0e5769

File tree

5 files changed

+31
-9
lines changed

5 files changed

+31
-9
lines changed

boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
&lcdic {
1818
status = "okay";
1919
nxp,swap-bytes;
20+
/* Raise the timer0 ratio to enable longer reset delay */
21+
nxp,timer0-ratio = <15>;
2022
/*
2123
* Settings to connect this display:
2224
* Populate the following resistors:

boards/shields/adafruit_2_8_tft_touch_v2/boards/rd_rw612_bga.overlay

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,8 @@
2222
&lcdic {
2323
/* Byte swapping not supported for this display */
2424
/delete-property/ nxp,swap-bytes;
25+
/* Set timer0 ratio to enable longer resets */
26+
nxp,timer0-ratio = <15>;
2527

2628
/*
2729
* Settings to connect this display:

boards/shields/lcd_par_s035/boards/rd_rw612_bga.overlay

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -92,4 +92,6 @@
9292
/* Set pulse width for write active and write inactive to min value */
9393
nxp,write-active-cycles = <1>;
9494
nxp,write-inactive-cycles = <1>;
95+
/* Raise the timer0 ratio to enable longer reset delay */
96+
nxp,timer0-ratio = <15>;
9597
};

drivers/mipi_dbi/mipi_dbi_nxp_lcdic.c

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,8 @@ struct mipi_dbi_lcdic_config {
7474
bool swap_bytes;
7575
uint8_t write_active_min;
7676
uint8_t write_inactive_min;
77+
uint8_t timer0_ratio;
78+
uint8_t timer1_ratio;
7779
};
7880

7981
#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA
@@ -125,12 +127,6 @@ struct mipi_dbi_lcdic_data {
125127
#define LCDIC_TX_FIFO_THRESH 0x3
126128
#endif
127129

128-
/* Timer0 and Timer1 bases. We choose a longer timer0 base to enable
129-
* long reset periods
130-
*/
131-
#define LCDIC_TIMER0_RATIO 0xF
132-
#define LCDIC_TIMER1_RATIO 0x9
133-
134130
/* After LCDIC is enabled or disabled, there should be a wait longer than
135131
* 5x the module clock before other registers are read
136132
*/
@@ -595,7 +591,7 @@ static int mipi_dbi_lcdic_reset(const struct device *dev, k_timeout_t delay)
595591
&lcdic_freq)) {
596592
return -EIO;
597593
}
598-
rst_width = (delay_ms * (lcdic_freq)) / ((1 << LCDIC_TIMER0_RATIO) * MSEC_PER_SEC);
594+
rst_width = (delay_ms * (lcdic_freq)) / ((1 << config->timer0_ratio) * MSEC_PER_SEC);
599595
/* If rst_width is larger than max value supported by hardware,
600596
* increase the pulse count (rounding up)
601597
*/
@@ -664,8 +660,8 @@ static int mipi_dbi_lcdic_init(const struct device *dev)
664660
LCDIC_TO_CTRL_CMD_SHORT_TO_MASK);
665661

666662
/* Ensure LCDIC timer ratios are at reset values */
667-
base->TIMER_CTRL = LCDIC_TIMER_CTRL_TIMER_RATIO1(LCDIC_TIMER1_RATIO) |
668-
LCDIC_TIMER_CTRL_TIMER_RATIO0(LCDIC_TIMER0_RATIO);
663+
base->TIMER_CTRL = LCDIC_TIMER_CTRL_TIMER_RATIO1(config->timer1_ratio) |
664+
LCDIC_TIMER_CTRL_TIMER_RATIO0(config->timer0_ratio);
669665

670666
#ifdef CONFIG_MIPI_DBI_NXP_LCDIC_DMA
671667
/* Attach the LCDIC DMA request signal to the DMA channel we will
@@ -807,6 +803,8 @@ static void mipi_dbi_lcdic_isr(const struct device *dev)
807803
DT_INST_PROP(n, nxp_write_active_cycles), \
808804
.write_inactive_min = \
809805
DT_INST_PROP(n, nxp_write_inactive_cycles), \
806+
.timer0_ratio = DT_INST_PROP(n, nxp_timer0_ratio), \
807+
.timer1_ratio = DT_INST_PROP(n, nxp_timer1_ratio), \
810808
}; \
811809
static struct mipi_dbi_lcdic_data mipi_dbi_lcdic_data_##n = { \
812810
LCDIC_DMA_CHANNELS(n) \

dts/bindings/mipi-dbi/nxp,lcdic.yaml

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,3 +46,21 @@ properties:
4646
Set minimum count of write active cycles, as a multiple of the module
4747
clock frequency. This controls the length of the active period of the
4848
WRX signal. Default is IP reset value. Only valid in 8080 mode.
49+
50+
nxp,timer0-ratio:
51+
type: int
52+
default: 8
53+
description: |
54+
Ratio for timer0, used for setting timer0 period (which is used for reset
55+
and TX/RX short command timeout). Formula is:
56+
timer0_period = (2 ^ timer0_ratio) / lcdic_freq
57+
Default is IP reset value
58+
59+
nxp,timer1-ratio:
60+
type: int
61+
default: 9
62+
description: |
63+
Ratio for timer1, used for setting timer1 period (which is used for TE
64+
wait time, timeout, and long command timeout). Formula is:
65+
timer1_period = (2 ^ timer1_ratio) * timer0_period
66+
Default is IP reset value

0 commit comments

Comments
 (0)