xtensa: ADSP: Intel: fix booting on APL with XCC

When built with XCC for Apollolake, Zephyr fails to boot with the
default multi-core option enabled. Invalidate cache before reading
the firmware image to fix that.

Signed-off-by: Guennadi Liakhovetski <[email protected]>

Author: lyakh

soc/xtensa/intel_adsp/common/bootloader/boot_loader.c

@@ -68,6 +68,7 @@ static inline void bmemcpy(void *dest, void *src, size_t bytes)
 	uint32_t *s = src;
 	int i;
 
+	z_xtensa_cache_inv(src, bytes);
 	for (i = 0; i < (bytes >> 2); i++)
 		d[i] = s[i];
 
@@ -167,10 +168,13 @@ static void parse_manifest(void)
 	struct sof_man_module *mod;
 	int i;
 
+	z_xtensa_cache_inv(hdr, sizeof(*hdr));
+
 	/* copy module to SRAM  - skip bootloader module */
 	for (i = MAN_SKIP_ENTRIES; i < hdr->num_module_entries; i++) {
 
 		mod = (void *)((uintptr_t)desc + SOF_MAN_MODULE_OFFSET(i));
+		z_xtensa_cache_inv(mod, sizeof(*mod));
 		parse_module(hdr, mod);
 	}
 }