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100 | 100 | <53 0 &gpioj 12 0>, /* LCD_BL_CTRL */
|
101 | 101 | <57 0 &gpiog 3 0>; /* DSI_RESET */
|
102 | 102 | };
|
| 103 | + |
| 104 | + dcmi_camera_connector: connector_dcmi_camera { |
| 105 | + compatible = "st,stm32-dcmi-camera-fpu-330zh"; |
| 106 | + #gpio-cells = <2>; |
| 107 | + gpio-map-mask = <0xffffffff 0xffffffc0>; |
| 108 | + gpio-map-pass-thru = <0 0x3f>; |
| 109 | + gpio-map = <3 0 &gpiod 12 0>, /* I2C4_SCL */ |
| 110 | + <4 0 &gpiod 13 0>, /* I2C4_SDA */ |
| 111 | + /* RESET is directly connected to MCU reset */ |
| 112 | + <6 0 &gpioj 14 0>, /* PWDN_EN */ |
| 113 | + <12 0 &gpiob 7 0>, /* DCMI_VSYNC */ |
| 114 | + <14 0 &gpioa 4 0>, /* DCMI_HSYNC */ |
| 115 | + <16 0 &gpioa 6 0>, /* DCMI_PIXCK */ |
| 116 | + <20 0 &gpiob 9 0>, /* DCMI_D7 */ |
| 117 | + <21 0 &gpiob 8 0>, /* DCMI_D6 */ |
| 118 | + <22 0 &gpiod 3 0>, /* DCMI_D5 */ |
| 119 | + <23 0 &gpioc 11 0>, /* DCMI_D4 */ |
| 120 | + <24 0 &gpioc 9 0>, /* DCMI_D3 */ |
| 121 | + <25 0 &gpiog 10 0>, /* DCMI_D2 */ |
| 122 | + <26 0 &gpioc 7 0>, /* DCMI_D1 */ |
| 123 | + <27 0 &gpioc 6 0>; /* DCMI_D0 */ |
| 124 | + }; |
103 | 125 | };
|
104 | 126 |
|
105 | 127 | &rcc {
|
|
132 | 154 | &mailbox {
|
133 | 155 | status = "okay";
|
134 | 156 | };
|
| 157 | + |
| 158 | +st_cam_i2c: &i2c4 {}; |
| 159 | + |
| 160 | +st_cam_dvp: &dcmi { |
| 161 | + pinctrl-0 = <&dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9 |
| 162 | + &dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9 |
| 163 | + &dcmi_pixclk_pa6 &dcmi_hsync_pa4 &dcmi_vsync_pb7>; |
| 164 | + |
| 165 | + pinctrl-names = "default"; |
| 166 | +}; |
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